riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Commit Graph

  • 0a6c05a5d8 connect top level interrupts to coreplex Colin Schmidt 2016-08-18 15:52:06 -0700
  • 91a97d6773 add some more comments to describe the new device system Howard Mao 2016-08-18 15:06:55 -0700
  • 1b6fa70b5c Add test for external TL clients (bus mastering) Howard Mao 2016-08-18 14:25:55 -0700
  • 18982d7351 add default addrMapEntry definition which throws exception Howard Mao 2016-08-18 12:29:41 -0700
  • f7c42499bb allow ExtraDevices to have client ports as well as MMIO ports Howard Mao 2016-08-18 12:14:41 -0700
  • d771f37e7e rename BusPorts to ExternalClients Howard Mao 2016-08-18 10:54:24 -0700
  • 10190197c3 allow coreplex to take in more than 1 bus port Howard Mao 2016-08-18 10:34:01 -0700
  • de316643d1 Merge pull request #205 from ucb-bar/configurable_memsize David Biancolin 2016-08-17 18:33:56 -0700
  • 29600f64ec make memsize configurable David Biancolin 2016-08-17 16:31:34 -0700
  • 5164f947c0 Validate mstatus.mpp/dcsr.prv values on MRET/DRET Andrew Waterman 2016-08-17 15:02:27 -0700
  • 35fbbfc70d put test harness on the heap in emulator Howard Mao 2016-08-16 14:50:40 -0700
  • ed827678ac Write test harness in Chisel Andrew Waterman 2016-08-15 22:03:03 -0700
  • 2d1d7266f5 Fix RV64 badaddr value on instruction faults with large addresses Andrew Waterman 2016-08-15 17:34:56 -0700
  • 38e0967816 strip DMA and RoCC CSRs out of rocket and uncore (#201) Howard Mao 2016-08-15 23:08:55 -0700
  • 47a0c880a4 make sure TLId set in Periphery Howard Mao 2016-08-15 13:58:23 -0700
  • e939af88aa explicitly set TLId for bus TL ports Howard Mao 2016-08-15 12:45:24 -0700
  • 2c39f039b5 make external address map order overrideable Howard Mao 2016-08-15 11:40:28 -0700
  • fb476d193c refactor main App for better code re-use Howard Mao 2016-08-11 16:15:23 -0700
  • a756856d84 make sure coreplex sources included in make dependencies Howard Mao 2016-08-11 14:27:03 -0700
  • e0ae039235 fix config string generation for extra devices Howard Mao 2016-08-11 10:44:32 -0700
  • 647dbefd9b split coreplex off into separate package Howard Mao 2016-08-10 17:20:00 -0700
  • 163cba6a85 make sure all regressions actually run Howard Mao 2016-08-10 11:40:58 -0700
  • 4bfa7ceb6a unit tests in Coreplex instead of Tile Howard Mao 2016-08-10 11:26:14 -0700
  • 571d579b86 get unit tests working again Howard Mao 2016-08-10 11:23:07 -0700
  • 0ee1ce4366 separate Coreplex and TopLevel parameter traits Howard Mao 2016-08-10 09:49:56 -0700
  • f95d319162 don't use secondary external address map; collapse submap instead Howard Mao 2016-08-09 22:19:08 -0700
  • 2645f74af2 clean up addrmap flatten function Howard Mao 2016-08-09 22:14:32 -0700
  • 33f13d5c49 don't repeat external addr map base Howard Mao 2016-08-09 21:20:54 -0700
  • 3ea2f4a6c4 refactor top-level into coreplex and platform Howard Mao 2016-08-09 18:26:52 -0700
  • 993da60f2c relax address map alignment requirement Howard Mao 2016-08-09 18:25:32 -0700
  • 33d5905c50 don't synthesize vsim verilog in Travis Howard Mao 2016-08-09 18:24:59 -0700
  • 405294167f fix TL -> Nasti converter w id Howard Mao 2016-08-09 15:05:46 -0700
  • 2906c75167 Remove fsim, as it is the same as vsim, modulo CONFIG Andrew Waterman 2016-08-09 15:42:22 -0700
  • 1b8f919db2 Remove unused CoreName parameter Andrew Waterman 2016-08-09 15:24:59 -0700
  • 458520c8f6 Use a generic UInt for TileLink op sizes, rather than MT_xx enum Andrew Waterman 2016-08-09 14:39:06 -0700
  • a857b08c59 [rocket] compute D$ tag bits based upon # of arbiter ports Andrew Waterman 2016-08-09 13:08:00 -0700
  • 2a5aeeae24 add sbt pack plugin (#197) Howard Mao 2016-08-08 19:31:03 -0700
  • dd1fed41b6 generate BootROM contents from assembly code Howard Mao 2016-08-05 11:07:42 -0700
  • dab96096b4 Add firrtl build dependencies Palmer Dabbelt 2016-08-05 14:45:00 -0700
  • 9fa5b228b2 allow extra devices and top-level ports to be added without changing RocketChip.scala Howard Mao 2016-08-04 12:42:07 -0700
  • 9c4e57aea5 example Rocc accelerator fixes Howard Mao 2016-08-04 11:17:13 -0700
  • 410e3e5366 make sure TraceGen gets correct addresses Howard Mao 2016-08-04 11:08:25 -0700
  • 0a85e92652 Allow additional internal MMIO devices to be created without changing BaseConfig Howard Mao 2016-08-03 16:33:30 -0700
  • cc0f8962fb [rocket] take physical memory attribute check off critical path Andrew Waterman 2016-08-02 15:11:48 -0700
  • 76f33d88a6 [rocket] Respect physical memory protection during page table walks Andrew Waterman 2016-08-02 14:51:11 -0700
  • 5d4f6383f2 [rocket] Automatically kill D$ access on address exceptions Andrew Waterman 2016-08-02 15:24:19 -0700
  • b54db0ba23 [rocket] don't update BTB on not-taken branches Andrew Waterman 2016-08-02 15:23:40 -0700
  • 64bde1060c [rocket] remove unused code in ibuf Andrew Waterman 2016-08-02 14:52:55 -0700
  • 2ce702dc0a [rocket] fix PTW critical path Andrew Waterman 2016-08-02 14:39:33 -0700
  • 7e9d139e49 [rocket] remove rocket-specific require() from HasCoreParameters Andrew Waterman 2016-08-02 14:38:33 -0700
  • 791a27748b Update firrtl and remove firrtl hack in plic Andrew Waterman 2016-08-02 14:37:59 -0700
  • f04aefc95c get rid of deprecated ZynqAdapter Howard Mao 2016-08-02 13:14:20 -0700
  • 63b814fcd7 only run the important (high coverage) tests in regression suite Howard Mao 2016-08-01 19:07:03 -0700
  • b7723f1ff8 make unit tests local to the packages being tested Howard Mao 2016-08-01 16:05:24 -0700
  • 98eede0505 some refactoring in RocketChip top-level Howard Mao 2016-08-01 11:02:59 -0700
  • 55c992bb3a Use FoldRight() instead of for loop Megan Wachs 2016-08-01 16:56:33 -0700
  • 8db2e8829f Allow aggregate CONFIG on Command Line Megan Wachs 2016-08-01 14:24:16 -0700
  • fe670e5421 Stop using deprecated FileSystemUtilities to create files Andrew Waterman 2016-07-31 18:04:56 -0700
  • 832e56d3c7 Fix toBits/toUInt/toSInt deprecation warnings Andrew Waterman 2016-07-31 17:13:52 -0700
  • a6e009d8de [rocket] Fix frontend mask when fetchWidth == 1 Andrew Waterman 2016-07-31 15:21:17 -0700
  • c49dad2e9d Improve PTW QoR Andrew Waterman 2016-07-29 17:52:56 -0700
  • cc635c386f Make Chisel3 the default version for SBT Andrew Waterman 2016-07-29 17:47:30 -0700
  • 4465260469 Update README.md mwachs5 2016-07-29 15:04:22 -0700
  • 058396aefe [rocket] Implement RVC Andrew Waterman 2016-07-29 16:36:07 -0700
  • c465120610 [rocket] use more standard pattern for computing integer min Andrew Waterman 2016-07-29 15:19:09 -0700
  • ffac86b041 [rocket] only write badaddr on certain exceptions Andrew Waterman 2016-07-29 15:18:39 -0700
  • 0d3d9fca25 [rocket] Allow zapping of BTB entries Andrew Waterman 2016-07-29 15:01:05 -0700
  • 8e0392f24b [rocket] don't hard-code instruction width in BHT Andrew Waterman 2016-07-29 14:59:04 -0700
  • f34b0b0447 make sure L2 tracker doesn't read data array again if data buffer already filled Howard Mao 2016-07-29 16:47:31 -0700
  • 2891eb879a add MergedPutRegression to uncover merged put after release bug in L2 Howard Mao 2016-07-29 16:42:28 -0700
  • 064020bdd7 make sure Memtest generators write different data to each address Howard Mao 2016-07-29 14:22:46 -0700
  • 5a3beca097 add RepeatedGetRegression to uncover L2 merged get miss bug Howard Mao 2016-07-28 19:58:47 -0700
  • cb86aaa46b fix trace generator addresses Howard Mao 2016-07-28 17:56:14 -0700
  • 8a7fc75b53 fix metadata race in blocking L1 DCache Andrew Waterman 2016-07-28 17:54:28 -0700
  • bd5972503f move groundtest/scripts to top-level scripts/ Howard Mao 2016-07-28 11:36:55 -0700
  • 478f494626 Merge remote-tracking branch 'groundtest/master' into mono-repo Howard Mao 2016-07-28 11:28:06 -0700
  • a5b88d0bdc Merge remote-tracking branch 'junctions/master' into mono-repo Howard Mao 2016-07-28 11:27:47 -0700
  • 373fd427dc Merge remote-tracking branch 'rocket/master' into mono-repo Howard Mao 2016-07-28 11:27:29 -0700
  • ce242b8f3f Merge remote-tracking branch 'uncore/master' into mono-repo Howard Mao 2016-07-28 11:23:31 -0700
  • aefba04fb3 get rid of submodules in preparation for merging Howard Mao 2016-07-28 11:21:08 -0700
  • 6de2a3e3b1 get rid of fpga-zynq submodule Howard Mao 2016-07-28 11:07:47 -0700
  • fe51a35fa9 a few more submodule bumps Howard Mao 2016-07-28 09:25:59 -0700
  • bf35f980a6 make sure PTE cache is power of 2 in size to satisfy PseudoLRU requirement Howard Mao 2016-07-27 18:40:38 -0700
  • fbcc7317cf make sure PseudoLRU is given power of 2 ways Howard Mao 2016-07-27 18:39:33 -0700
  • 15d1aa9346 make sure TrackerAllocationIO addr_block has correct direction set Howard Mao 2016-07-27 16:47:22 -0700
  • 9c89290efc fix LRSC issue (fixes issue #86) Howard Mao 2016-07-26 22:25:04 -0700
  • 0bd7ef1278 re-enable SCs inflight with other requests Howard Mao 2016-07-26 22:21:41 -0700
  • df07771fa0 add uncached noise generator to TraceGen Howard Mao 2016-07-26 12:41:36 -0700
  • dcfcac9530 fix LRSC issue (RocketChip issue #86) Howard Mao 2016-07-26 17:20:20 -0700
  • ecd1af326c fix L2 deadlock bug and add more advanced trace generator Howard Mao 2016-07-26 12:43:08 -0700
  • 82bbbf908d Fix L2 Writeback deadlock issue Howard Mao 2016-07-26 12:31:08 -0700
  • 1063d90993 make sure L1 and L2 agree on coherence policy Howard Mao 2016-07-25 12:20:49 -0700
  • 6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode Howard Mao 2016-07-22 11:36:45 -0700
  • 11ec5b2cf4 bram: don't deal with multibeat; rely on the fragmenter Wesley W. Terpstra 2016-07-20 16:05:28 -0700
  • a52d418439 fragmenter: support multi-beat get/put via fragmenting to single-beat operations Wesley W. Terpstra 2016-07-20 13:58:49 -0700
  • 51edd19e85 add U bit to misa register Howard Mao 2016-07-22 14:22:51 -0700
  • 75347eed56 some fixes and cleanup to stateless bridge Howard Mao 2016-07-21 18:33:46 -0700
  • 9168f35971 clean up the requirements in StatelessBridge Howard Mao 2016-07-21 18:31:19 -0700
  • a43ad522dc add clock override to tile constructor (#42) Colin Schmidt 2016-07-21 20:56:52 -0400
  • 12067a3b8d make sure outer probe and finish lines are disconnected Howard Mao 2016-07-21 15:07:25 -0700