Merge pull request #205 from ucb-bar/configurable_memsize
make memsize configurable
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commit
de316643d1
@ -33,7 +33,7 @@ class BasePlatformConfig extends Config (
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collapse = true)
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lazy val globalAddrMap = {
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val memBase = 0x80000000L
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val memSize = 0x10000000L
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val memSize = site(ExtMemSize)
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val intern = AddrMapEntry("int", internalIOAddrMap)
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val extern = AddrMapEntry("ext", externalAddrMap)
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@ -44,7 +44,6 @@ class BasePlatformConfig extends Config (
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AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
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Dump("MEM_BASE", addrMap("mem").start)
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Dump("MEM_SIZE", memSize)
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addrMap
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}
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def makeConfigString() = {
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@ -149,6 +148,7 @@ class BasePlatformConfig extends Config (
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case AsyncMemChannels => false
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case ConfigString => makeConfigString()
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case GlobalAddrMap => globalAddrMap
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case _ => throw new CDEMatchError
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@ -182,6 +182,12 @@ class WithNMemoryChannels(n: Int) extends Config(
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}
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)
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class WithExtMemSize(n: Long) extends Config(
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(pname,site,here) => pname match {
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case ExtMemSize => Dump("MEM_SIZE", n)
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case _ => throw new CDEMatchError
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}
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)
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class WithAHB extends Config(
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(pname, site, here) => pname match {
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case TMemoryChannels => BusType.AHB
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@ -43,6 +43,8 @@ case object ExtIOAddrMapEntries extends Field[Seq[AddrMapEntry]]
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case object BuildCoreplex extends Field[Parameters => Coreplex]
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/** Function for connecting coreplex extra ports to top-level extra ports */
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case object ConnectExtraPorts extends Field[(Bundle, Bundle, Parameters) => Unit]
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/** Specifies the size of external memory */
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case object ExtMemSize extends Field[Long]
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/** Utility trait for quick access to some relevant parameters */
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trait HasTopLevelParameters {
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