riscv/rocket-chip
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  • 7afd630d3e add multiclock support to Coreplex Yunsup Lee 2016-09-21 16:54:35 -0700
  • 8e63f4a1a5 Remove ClockToSignal and vice-versa Andrew Waterman 2016-09-21 16:17:14 -0700
  • 2ab61f1a71 Chisel implicit clock is now named clock, not clk Andrew Waterman 2016-09-21 16:16:47 -0700
  • 335e866176 [unittest] Parallelize UnitTestSuite (#319) Henry Cook 2016-09-21 13:05:22 -0700
  • 12d0c00822 Fix mtime RegField handling Andrew Waterman 2016-09-20 15:00:52 -0700
  • 6f6480ad9f Merge pull request #303 from ucb-bar/testharness-refactor Henry Cook 2016-09-20 14:45:05 -0700
  • 40f6f31611 [unittest] further refactor unittest framework Henry Cook 2016-09-20 14:14:30 -0700
  • ed91e9a89b Merge remote-tracking branch 'origin' into testharness-refactor Henry Cook 2016-09-20 13:03:21 -0700
  • b97a0947a9 [rocketchip] enable piecewise Generator output Henry Cook 2016-09-20 12:57:56 -0700
  • 74fc7c5803 Merge pull request #315 from ucb-bar/fix-addrmap-error-msg Howard Mao 2016-09-19 19:39:56 -0700
  • 1a09e46f69 Merge branch 'master' into fix-addrmap-error-msg Yunsup Lee 2016-09-19 18:08:58 -0700
  • 15e7041ccb Merge pull request #316 from ucb-bar/dynamic-reset-vector Yunsup Lee 2016-09-19 18:00:25 -0700
  • 3b38736a8e Make BaseTopModule and BaseTopModule abstract Andrew Waterman 2016-09-19 16:50:04 -0700
  • d0572d6aab Allow reset vector to be set dynamically Andrew Waterman 2016-09-19 16:45:57 -0700
  • e6c1bcfedd Expose carry-out bits from WideCounter Andrew Waterman 2016-09-19 15:54:17 -0700
  • 2961d92244 [testharness] vsim makefrag cleanup Henry Cook 2016-09-19 13:46:45 -0700
  • 1b26d78114 correctly print out the addrmap overlapping error message Yunsup Lee 2016-09-19 13:34:58 -0700
  • df442ed82c [rocketchip] avoid pending merge conflict] Henry Cook 2016-09-19 13:24:01 -0700
  • ddcf1b4099 Use PROJECT rather than MODEL in name of binary and generated src files. Henry Cook 2016-09-19 13:23:17 -0700
  • 7b8aa6c839 [rocketchip] split out Base and Example tops Henry Cook 2016-09-19 11:00:13 -0700
  • 7ff7076dab Merge pull request #310 from ucb-bar/rxia-testharness-refactor Henry Cook 2016-09-19 10:22:49 -0700
  • f0debb89e4 Merge pull request #314 from ucb-bar/widecounter-reset Andrew Waterman 2016-09-18 22:37:40 -0700
  • a49814c667 Allow WideCounter to not be reset Andrew Waterman 2016-09-18 18:45:51 -0700
  • aa956c0108 Merge pull request #312 from ucb-bar/tl2-cheap-address-decode Wesley W. Terpstra 2016-09-17 17:37:03 -0700
  • 9817a00ed9 tilelink2: Fuzzer should check address validity before injection Wesley W. Terpstra 2016-09-17 17:07:21 -0700
  • b11839f5a1 tilelink2: differentiate fast/safe address lookup cases Wesley W. Terpstra 2016-09-17 17:04:18 -0700
  • b4baae4214 tilelink2: minimize Xbar decode logic Wesley W. Terpstra 2016-09-17 16:13:46 -0700
  • 76d8ed6a69 tilelink2: remove 'strided'; !contiguous is clearer Wesley W. Terpstra 2016-09-17 15:31:35 -0700
  • fa0f119f3c tilelink2: consider the implications of negative address mask Wesley W. Terpstra 2016-09-17 15:27:39 -0700
  • e437508548 tilelink2: track interrupt connectivity like in TL2 Wesley W. Terpstra 2016-09-17 13:56:35 -0700
  • fd3ac4653c Merge pull request #311 from ucb-bar/rom-executable Wesley W. Terpstra 2016-09-17 01:28:52 -0700
  • 01c1886b9d Utils: cacheable only if there is a cache manager Wesley W. Terpstra 2016-09-17 00:56:21 -0700
  • 6c3269a1d8 SRAM: optionally (default: true) executable Wesley W. Terpstra 2016-09-17 00:19:37 -0700
  • e749558190 ROM: optionally (default: true) executable Wesley W. Terpstra 2016-09-17 00:19:09 -0700
  • c70045b8b3 Utils: express cacheability from TL2 to TL1 Wesley W. Terpstra 2016-09-17 00:16:40 -0700
  • e3d2bd3323 Top: print memory region properties, RWX [C] Wesley W. Terpstra 2016-09-17 00:16:00 -0700
  • 75c73fce37 Merge pull request #309 from ucb-bar/tl2-addrmap Wesley W. Terpstra 2016-09-16 19:09:22 -0700
  • 5c858685aa Utils: support managers with multiple addresses Wesley W. Terpstra 2016-09-16 18:03:49 -0700
  • 3fdf40c088 Change implicit argument to explicit. Richard Xia 2016-09-16 17:47:31 -0700
  • a9382b3116 Periphery: test bench looks for "testram" Wesley W. Terpstra 2016-09-16 17:47:20 -0700
  • b5ce6150c7 Periphery: dynamically create address map + config string for TL2 Wesley W. Terpstra 2016-09-16 17:27:49 -0700
  • 8876d83640 Prci: preserve Andrew's preferred clint name Wesley W. Terpstra 2016-09-16 17:26:50 -0700
  • a357c1d42e tilelink2: create DTS for devices automagically Wesley W. Terpstra 2016-09-16 17:26:14 -0700
  • 2587234838 tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters Wesley W. Terpstra 2016-09-16 17:25:22 -0700
  • 915a929af1 tilelink2: Nodes can now mix context into parameters Wesley W. Terpstra 2016-09-16 17:25:00 -0700
  • 63f13ae7ce Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor Richard Xia 2016-09-16 17:10:52 -0700
  • 503ce14c98 Merge pull request #307 from ucb-bar/address-shrink Wesley W. Terpstra 2016-09-16 16:55:35 -0700
  • dae0918c85 tilelink2 RegisterRouter: support undefZero Wesley W. Terpstra 2016-09-16 14:54:30 -0700
  • f0f553f227 tilelink2 RegisterRouterTest: work around firrtl warning Wesley W. Terpstra 2016-09-16 14:49:43 -0700
  • 3fcc1a4460 tilelink2 RegisterRouterTest: don't couple fire into helpers Wesley W. Terpstra 2016-09-16 14:46:37 -0700
  • 2210e71f42 tilelink2 AddressDecoder: validate output of optimization Wesley W. Terpstra 2016-09-16 00:49:05 -0700
  • 023a54f122 tilelink2 AddressDecoder: improved heuristic Wesley W. Terpstra 2016-09-16 00:27:26 -0700
  • 4abba87b61 bump firrtl to include empty module fix for vivado (#306) Yunsup Lee 2016-09-16 15:53:53 -0700
  • 86b70c8c59 Rename PRCI to CoreplexLocalInterrupter Andrew Waterman 2016-09-16 14:26:34 -0700
  • 4b1de82c1d RegField: separate UInt=>bytes and bytes=>regs Wesley W. Terpstra 2016-09-16 14:19:42 -0700
  • 943c36954d tilelink2 RegField: .bytes should update more than one byte! Wesley W. Terpstra 2016-09-16 13:45:05 -0700
  • 6134384da4 Fix deprecation warnings Andrew Waterman 2016-09-16 12:43:36 -0700
  • a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305) mwachs5 2016-09-16 13:50:09 -0700
  • a94b4af92d Simplify AsyncResetRegVec and make AsyncResetReg companion object Andrew Waterman 2016-09-15 14:45:47 -0700
  • 198a2d7022 Merge pull request #302 from ucb-bar/tl2-mmio Yunsup Lee 2016-09-15 22:45:35 -0700
  • dd19e0911e tilelink2: handle bus width=1 Wesley W. Terpstra 2016-09-15 22:13:08 -0700
  • e1d7f6d7df PRCI: always use bus width >= XLen Wesley W. Terpstra 2016-09-15 22:06:39 -0700
  • 2c53620275 chisel3: bump for Irrevocable(Decoupled) constructor Wesley W. Terpstra 2016-09-15 21:28:16 -0700
  • 0e80f7fd0f HintHandler: don't violate Irrevocable rules Wesley W. Terpstra 2016-09-15 21:27:49 -0700
  • f05222a072 testconfigs: disable atomics until AtomicAbsorber finished Wesley W. Terpstra 2016-09-15 21:15:30 -0700
  • 38a9421c75 Comparator: don't compare addr_beat when it's irrelevant Wesley W. Terpstra 2016-09-15 18:55:58 -0700
  • 669e3b0d96 Regression: fix-up address lookup Wesley W. Terpstra 2016-09-15 16:16:36 -0700
  • 30fa4ea956 RegisterRouter: compress register mapping for sparse devices Wesley W. Terpstra 2016-09-15 15:52:50 -0700
  • 6b1c57aedc tilelink2: compute minimal decisive mask Wesley W. Terpstra 2016-09-15 14:47:44 -0700
  • fb24e847fd rocketchip: globals are for sissies Wesley W. Terpstra 2016-09-15 00:38:46 -0700
  • 644f8fe974 rocketchip: switch to TL2 mmio + port PRCI Wesley W. Terpstra 2016-09-14 18:09:27 -0700
  • 91e7da4de3 tilelink2: make RegisterRouter constructor args public Wesley W. Terpstra 2016-09-14 23:19:03 -0700
  • 3875e11b26 tilelink2: RegField splits up big registers Wesley W. Terpstra 2016-09-14 23:06:49 -0700
  • 5c8e52ca32 devices: TL2 version of ROM Wesley W. Terpstra 2016-09-14 20:40:00 -0700
  • 3f30e11f16 tilelink2: Legacy, manager_xact_id does not matter for uncached Wesley W. Terpstra 2016-09-14 19:52:03 -0700
  • ddd93871d8 tilelink2: add an executable manager parameter Wesley W. Terpstra 2016-09-14 18:08:49 -0700
  • 9442958d67 tilelink2: allow := on nodes outside the tilelink2 package Wesley W. Terpstra 2016-09-14 18:08:18 -0700
  • f2fe437fa4 Use CDEMatchError for improved performance (#304) Jack Koenig 2016-09-15 19:47:18 -0700
  • 851a336db4 [unittest] split out Config and TestHarness into separate files, minimize imports Henry Cook 2016-09-15 14:25:47 -0700
  • 245f8ab76b [util] move LatencyPipe into util Henry Cook 2016-09-15 13:30:34 -0700
  • a70d8c9821 Merge remote-tracking branch 'origin/master' into testharness-refactor Henry Cook 2016-09-15 13:27:07 -0700
  • be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs Henry Cook 2016-09-15 13:04:01 -0700
  • c6f252a913 Remove Option from success flag in coreplex; just use a sane default. Henry Cook 2016-09-15 12:19:22 -0700
  • 9e2b0aad65 Revert "allow MODEL to be something other than TestHarness" Henry Cook 2016-09-15 11:53:05 -0700
  • 888f6a2a55 Revert "move UnitTest back into rocketchip module" Henry Cook 2016-09-15 11:48:09 -0700
  • 29ce599ea2 Merge pull request #295 from ucb-bar/tl2-irrevocable Henry Cook 2016-09-15 11:33:05 -0700
  • 0a65238920 Merge branch 'master' into tl2-irrevocable Henry Cook 2016-09-15 10:30:50 -0700
  • 49863944c4 merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer Howard Mao 2016-09-13 11:24:05 -0700
  • f363f5f709 wrap TestHarness latency pipe in module Howard Mao 2016-09-13 15:34:42 -0700
  • f5db83a72f NTiles should not be a Knob Howard Mao 2016-09-13 11:29:26 -0700
  • 646527c88e use named constants to set AXI resp, cache, and prot fields Howard Mao 2016-09-13 10:47:36 -0700
  • f95b8c4ec2 move UnitTest back into rocketchip module Howard Mao 2016-09-14 20:05:37 -0700
  • bf253aaa97 allow MODEL to be something other than TestHarness Howard Mao 2016-09-14 20:04:33 -0700
  • 8550582f84 remove redundant verilator rule Howard Mao 2016-09-14 20:29:55 -0700
  • a304695ffd Add firrtl and verilog Makefile targets to vsim jackkoenig 2016-09-14 17:33:39 -0700
  • cde104b3fa [junctions] Removes the obsoleted SMI. Henry Cook 2016-09-14 18:04:24 -0700
  • 96110caca1 Merge pull request #291 from ucb-bar/move-bootrom Yunsup Lee 2016-09-14 19:51:16 -0700
  • ab3814dcee Merge branch 'master' into tl2-irrevocable Henry Cook 2016-09-14 19:00:17 -0700
  • e404bea2ee Merge branch 'master' into move-bootrom Yunsup Lee 2016-09-14 18:58:48 -0700
  • f2cb9da91a Merge pull request #296 from ucb-bar/split-unittest Yunsup Lee 2016-09-14 18:56:11 -0700