Henry Cook
Howard Mao
parent
96110caca1
commit
cde104b3fa
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@ -1,281 +0,0 @@
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package junctions
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import Chisel._
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import cde.Parameters
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class SmiReq(val dataWidth: Int, val addrWidth: Int) extends Bundle {
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val rw = Bool()
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val addr = UInt(width = addrWidth)
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val data = Bits(width = dataWidth)
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override def cloneType =
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new SmiReq(dataWidth, addrWidth).asInstanceOf[this.type]
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}
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/** Simple Memory Interface IO. Used to communicate with PCR and SCR
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* @param dataWidth the width in bits of the data field
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* @param addrWidth the width in bits of the addr field */
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class SmiIO(val dataWidth: Int, val addrWidth: Int) extends Bundle {
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val req = Decoupled(new SmiReq(dataWidth, addrWidth))
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val resp = Decoupled(Bits(width = dataWidth)).flip
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override def cloneType =
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new SmiIO(dataWidth, addrWidth).asInstanceOf[this.type]
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}
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abstract class SmiPeripheral extends Module {
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val dataWidth: Int
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val addrWidth: Int
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lazy val io = new SmiIO(dataWidth, addrWidth).flip
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}
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/** A simple sequential memory accessed through Smi */
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class SmiMem(val dataWidth: Int, val memDepth: Int) extends SmiPeripheral {
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// override
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val addrWidth = log2Up(memDepth)
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val mem = SeqMem(memDepth, Bits(width = dataWidth))
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val ren = io.req.fire() && !io.req.bits.rw
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val wen = io.req.fire() && io.req.bits.rw
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when (wen) { mem.write(io.req.bits.addr, io.req.bits.data) }
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val resp_valid = Reg(init = Bool(false))
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when (io.resp.fire()) { resp_valid := Bool(false) }
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when (io.req.fire()) { resp_valid := Bool(true) }
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io.resp.valid := resp_valid
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io.resp.bits := mem.read(io.req.bits.addr, ren)
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io.req.ready := !resp_valid
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}
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/** Arbitrate among several Smi clients
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* @param n the number of clients
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* @param dataWidth Smi data width
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* @param addrWidth Smi address width */
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class SmiArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
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extends Module {
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val io = new Bundle {
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val in = Vec(n, new SmiIO(dataWidth, addrWidth)).flip
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val out = new SmiIO(dataWidth, addrWidth)
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}
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val wait_resp = Reg(init = Bool(false))
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val choice = Reg(UInt(width = log2Up(n)))
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val req_arb = Module(new RRArbiter(new SmiReq(dataWidth, addrWidth), n))
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req_arb.io.in <> io.in.map(_.req)
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req_arb.io.out.ready := io.out.req.ready && !wait_resp
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io.out.req.bits := req_arb.io.out.bits
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io.out.req.valid := req_arb.io.out.valid && !wait_resp
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when (io.out.req.fire()) {
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choice := req_arb.io.chosen
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wait_resp := Bool(true)
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}
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when (io.out.resp.fire()) { wait_resp := Bool(false) }
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for ((resp, i) <- io.in.map(_.resp).zipWithIndex) {
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resp.bits := io.out.resp.bits
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resp.valid := io.out.resp.valid && choice === UInt(i)
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}
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io.out.resp.ready := io.in(choice).resp.ready
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}
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class SmiIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
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(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = new NastiReadIO().flip
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val smi = new SmiIO(dataWidth, addrWidth)
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}
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private val maxWordsPerBeat = nastiXDataBits / dataWidth
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private val wordCountBits = log2Up(maxWordsPerBeat)
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private val byteOffBits = log2Up(dataWidth / 8)
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private val addrOffBits = addrWidth + byteOffBits
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private def calcWordCount(size: UInt): UInt =
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(UInt(1) << (size - UInt(byteOffBits))) - UInt(1)
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val (s_idle :: s_read :: s_resp :: Nil) = Enum(Bits(), 3)
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val state = Reg(init = s_idle)
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val nWords = Reg(UInt(width = wordCountBits))
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val nBeats = Reg(UInt(width = nastiXLenBits))
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val addr = Reg(UInt(width = addrWidth))
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val id = Reg(UInt(width = nastiRIdBits))
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val byteOff = Reg(UInt(width = byteOffBits))
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val recvInd = Reg(init = UInt(0, wordCountBits))
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val sendDone = Reg(init = Bool(false))
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val buffer = Reg(init = Vec.fill(maxWordsPerBeat) { Bits(0, dataWidth) })
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io.nasti.ar.ready := (state === s_idle)
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io.smi.req.valid := (state === s_read) && !sendDone
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io.smi.req.bits.rw := Bool(false)
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io.smi.req.bits.addr := addr
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io.smi.resp.ready := (state === s_read)
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io.nasti.r.valid := (state === s_resp)
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io.nasti.r.bits := NastiReadDataChannel(
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id = id,
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data = buffer.asUInt,
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last = (nBeats === UInt(0)))
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when (io.nasti.ar.fire()) {
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when (io.nasti.ar.bits.size < UInt(byteOffBits)) {
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nWords := UInt(0)
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} .otherwise {
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nWords := calcWordCount(io.nasti.ar.bits.size)
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}
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nBeats := io.nasti.ar.bits.len
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addr := io.nasti.ar.bits.addr(addrOffBits - 1, byteOffBits)
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if (maxWordsPerBeat > 1)
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recvInd := io.nasti.ar.bits.addr(wordCountBits + byteOffBits - 1, byteOffBits)
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else
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recvInd := UInt(0)
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id := io.nasti.ar.bits.id
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state := s_read
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}
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when (io.smi.req.fire()) {
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addr := addr + UInt(1)
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sendDone := (nWords === UInt(0))
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}
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when (io.smi.resp.fire()) {
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recvInd := recvInd + UInt(1)
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nWords := nWords - UInt(1)
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buffer(recvInd) := io.smi.resp.bits
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when (nWords === UInt(0)) { state := s_resp }
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}
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when (io.nasti.r.fire()) {
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recvInd := UInt(0)
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sendDone := Bool(false)
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// clear all the registers in the buffer
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buffer.foreach(_ := Bits(0))
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nBeats := nBeats - UInt(1)
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state := Mux(io.nasti.r.bits.last, s_idle, s_read)
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}
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}
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class SmiIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = new NastiWriteIO().flip
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val smi = new SmiIO(dataWidth, addrWidth)
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}
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private val dataBytes = dataWidth / 8
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private val maxWordsPerBeat = nastiXDataBits / dataWidth
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private val byteOffBits = log2Floor(dataBytes)
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private val addrOffBits = addrWidth + byteOffBits
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private val nastiByteOffBits = log2Ceil(nastiXDataBits / 8)
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assert(!io.nasti.aw.valid || io.nasti.aw.bits.size >= UInt(byteOffBits),
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"Nasti size must be >= Smi size")
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val id = Reg(UInt(width = nastiWIdBits))
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val addr = Reg(UInt(width = addrWidth))
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val offset = Reg(UInt(width = nastiByteOffBits))
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def makeStrobe(offset: UInt, size: UInt, strb: UInt) = {
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val sizemask = (UInt(1) << (UInt(1) << size)) - UInt(1)
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val bytemask = strb & (sizemask << offset)
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Vec.tabulate(maxWordsPerBeat){i => bytemask(dataBytes * i)}.asUInt
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}
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val size = Reg(UInt(width = nastiXSizeBits))
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val strb = Reg(UInt(width = maxWordsPerBeat))
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val data = Reg(UInt(width = nastiXDataBits))
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val last = Reg(Bool())
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val s_idle :: s_data :: s_send :: s_ack :: s_resp :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
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io.nasti.aw.ready := (state === s_idle)
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io.nasti.w.ready := (state === s_data)
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io.smi.req.valid := (state === s_send) && strb(0)
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io.smi.req.bits.rw := Bool(true)
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io.smi.req.bits.addr := addr
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io.smi.req.bits.data := data(dataWidth - 1, 0)
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io.smi.resp.ready := (state === s_ack)
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io.nasti.b.valid := (state === s_resp)
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io.nasti.b.bits := NastiWriteResponseChannel(id)
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val jump = if (maxWordsPerBeat > 1)
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PriorityMux(strb(maxWordsPerBeat - 1, 1),
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(1 until maxWordsPerBeat).map(UInt(_)))
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else UInt(1)
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when (io.nasti.aw.fire()) {
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if (dataWidth == nastiXDataBits) {
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addr := io.nasti.aw.bits.addr(addrOffBits - 1, byteOffBits)
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} else {
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addr := Cat(io.nasti.aw.bits.addr(addrOffBits - 1, nastiByteOffBits),
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UInt(0, nastiByteOffBits - byteOffBits))
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}
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offset := io.nasti.aw.bits.addr(nastiByteOffBits - 1, 0)
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id := io.nasti.aw.bits.id
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size := io.nasti.aw.bits.size
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last := Bool(false)
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state := s_data
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}
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when (io.nasti.w.fire()) {
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last := io.nasti.w.bits.last
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strb := makeStrobe(offset, size, io.nasti.w.bits.strb)
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data := io.nasti.w.bits.data
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state := s_send
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}
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when (state === s_send) {
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when (io.smi.req.ready || !strb(0)) {
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strb := strb >> jump
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data := data >> Cat(jump, UInt(0, log2Up(dataWidth)))
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addr := addr + jump
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when (strb(0)) { state := s_ack }
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}
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}
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when (io.smi.resp.fire()) {
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state := Mux(strb === UInt(0),
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Mux(last, s_resp, s_data), s_send)
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}
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when (io.nasti.b.fire()) { state := s_idle }
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}
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/** Convert Nasti protocol to Smi protocol */
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class SmiIONastiIOConverter(val dataWidth: Int, val addrWidth: Int)
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(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val smi = new SmiIO(dataWidth, addrWidth)
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}
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require(isPow2(dataWidth), "SMI data width must be power of 2")
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require(dataWidth <= nastiXDataBits,
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"SMI data width must be less than or equal to NASTI data width")
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val reader = Module(new SmiIONastiReadIOConverter(dataWidth, addrWidth))
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reader.io.nasti <> io.nasti
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val writer = Module(new SmiIONastiWriteIOConverter(dataWidth, addrWidth))
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writer.io.nasti <> io.nasti
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val arb = Module(new SmiArbiter(2, dataWidth, addrWidth))
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arb.io.in(0) <> reader.io.smi
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arb.io.in(1) <> writer.io.smi
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io.smi <> arb.io.out
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}
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@ -1,59 +0,0 @@
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// See LICENSE for details
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package uncore.converters
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import cde.Parameters
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/** Convert TileLink protocol to Smi protocol */
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class SmiIOTileLinkIOConverter(val dataWidth: Int, val addrWidth: Int)
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(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val tl = (new ClientUncachedTileLinkIO).flip
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val smi = new SmiIO(dataWidth, addrWidth)
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}
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def decoupledNastiConnect(outer: NastiIO, inner: NastiIO) {
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outer.ar <> Queue(inner.ar)
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outer.aw <> Queue(inner.aw)
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outer.w <> Queue(inner.w)
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inner.r <> Queue(outer.r)
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inner.b <> Queue(outer.b)
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}
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val tl2nasti = Module(new NastiIOTileLinkIOConverter())
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val nasti2smi = Module(new SmiIONastiIOConverter(dataWidth, addrWidth))
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tl2nasti.io.tl <> io.tl
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decoupledNastiConnect(nasti2smi.io.nasti, tl2nasti.io.nasti)
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io.smi <> nasti2smi.io.smi
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}
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class SmiConverterTest(implicit val p: Parameters) extends unittest.UnitTest
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with HasTileLinkParameters {
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val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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val smiWidth = 32
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val smiDepth = 64
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val tlDepth = (smiWidth * smiDepth) / tlDataBits
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val smimem = Module(new SmiMem(smiWidth, smiDepth))
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val conv = Module(new SmiIOTileLinkIOConverter(
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smiWidth, log2Up(smiDepth))(outermostParams))
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val driver = Module(new DriverSet(
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(driverParams: Parameters) => {
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implicit val p = driverParams
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Seq(
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Module(new PutSweepDriver(tlDepth)),
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Module(new PutMaskDriver(smiWidth / 8)),
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Module(new PutBlockSweepDriver(tlDepth / tlDataBeats)),
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Module(new GetMultiWidthDriver))
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})(outermostParams))
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conv.io.tl <> driver.io.mem
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smimem.io <> conv.io.smi
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driver.io.start := io.start
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io.finished := driver.io.finished
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}
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@ -14,7 +14,6 @@ object JunctionsUnitTests {
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object UncoreUnitTests {
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def apply(implicit p: Parameters): Seq[UnitTest] =
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Seq(
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Module(new uncore.converters.SmiConverterTest),
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Module(new uncore.devices.ROMSlaveTest),
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Module(new uncore.devices.TileLinkRAMTest),
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Module(new uncore.tilelink2.TLFuzzRAMTest))
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Loading…
Reference in New Issue
Block a user