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Merge pull request #303 from ucb-bar/testharness-refactor 

TestHarness refactoring
This commit is contained in:
Henry Cook 2016-09-20 14:45:05 -07:00 committed by GitHub
parent 74fc7c5803 40f6f31611
commit 6f6480ad9f
26 changed files with 377 additions and 344 deletions
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8
Makefrag
View File

@ -6,6 +6,10 @@ endif
MODEL ?= TestHarness
PROJECT ?= rocketchip
CFG_PROJECT ?= $(PROJECT)
CONFIG ?= DefaultConfig
# TODO: For now must match rocketchip.Generator
long_name = $(PROJECT).$(CONFIG)
CXX ?= g++
CXXFLAGS := -O1
@ -50,7 +54,7 @@ bootrom_img = $(base_dir)/bootrom/bootrom.img
#---------------------------------------------------------------------
# sed uses -E (instead of -r) for BSD support
params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm
params_file = $(generated_dir)/$(long_name).prm
consts_header = $(generated_dir)/consts.$(CONFIG).h
$(consts_header): $(params_file)
echo "#ifndef __CONST_H__" > $@
@ -58,7 +62,7 @@ $(consts_header): $(params_file)
sed -E 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@
echo "#endif // __CONST_H__" >> $@
params_file_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).prm
params_file_debug = $(generated_dir_debug)/$(long_name).prm
consts_header_debug = $(generated_dir_debug)/consts.$(CONFIG).h
$(consts_header_debug): $(params_file_debug)
echo "#ifndef __CONST_H__" > $@

2
csrc/emulator.cc
View File

@ -65,7 +65,7 @@ int main(int argc, char** argv)
srand48(random_seed);
Verilated::randReset(2);
MODEL *tile = new MODEL;
VTestHarness *tile = new VTestHarness;
#if VM_TRACE
Verilated::traceEverOn(true); // Verilator must compute traced signals

5
emulator/Makefile
View File

@ -6,9 +6,6 @@ generated_dir_debug = $(abspath ./generated-src-debug)
sim_dir = .
output_dir = $(sim_dir)/output
BACKEND = c
CONFIG ?= DefaultConfig
include $(base_dir)/Makefrag
CXXSRCS := emulator SimDTM
@ -36,7 +33,7 @@ test:
#--------------------------------------------------------------------
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(generated_dir)/$(MODEL).$(CONFIG).d
-include $(generated_dir)/$(long_name).d
endif
$(output_dir)/%.run: $(output_dir)/% $(emu)

33
emulator/Makefrag-verilator
View File

@ -1,19 +1,18 @@
#--------------------------------------------------------------------
# Verilator Generation
#--------------------------------------------------------------------
firrtl = $(generated_dir)/$(MODEL).$(CONFIG).fir
firrtl_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
verilog = $(generated_dir)/$(MODEL).$(CONFIG).v
verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v
firrtl = $(generated_dir)/$(long_name).fir
firrtl_debug = $(generated_dir_debug)/$(long_name).fir
verilog = $(generated_dir)/$(long_name).v
verilog_debug = $(generated_dir_debug)/$(long_name).v
.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img)
$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img)
$(generated_dir_debug)/%.fir $(generated_dir_debug)/%.prm $(generated_dir_debug)/%.d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
@ -54,23 +53,23 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
-Wno-STMTDLY --x-assign unique \
-I$(base_dir)/vsrc \
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h -DMODEL=V$(MODEL)"
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
headers = $(wildcard $(base_dir)/csrc/*.h)
model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h
model_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG)/V$(MODEL).h
model_header = $(generated_dir)/$(long_name)/V$(MODEL).h
model_header_debug = $(generated_dir_debug)/$(long_name)/V$(MODEL).h
$(emu): $(verilog) $(cppfiles) $(headers) $(consts_header) $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
mkdir -p $(generated_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header)"
$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
$(MAKE) -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG) --trace \
$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(consts_header_debug) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir_debug)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug)"
$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
$(MAKE) -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk

35
regression/Makefile
View File

@ -39,22 +39,19 @@ $(error Set SUITE to the regression suite you want to run)
endif
ifeq ($(SUITE),RocketSuite)
MODEL=TestHarness
PROJECT=rocketchip
CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig TinyConfig
endif
ifeq ($(SUITE),GroundtestSuite)
MODEL=TestHarness
PROJECT=rocketchip
PROJECT=groundtest
CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtestConfig \
BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig
endif
ifeq ($(SUITE),UnittestSuite)
MODEL=UnitTestHarness
PROJECT=rocketchip
PROJECT=unittest
CONFIGS=UnitTestConfig
endif
@ -126,65 +123,65 @@ $(RISCV)/install.stamp:
# Builds the various simulators
stamps/%/emulator-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
date > $@
stamps/%/emulator-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV))
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
date > $@
stamps/%/emulator-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
date > $@
stamps/%/vsim-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
date > $@
stamps/%/vsim-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV))
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
date > $@
stamps/%/vsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
date > $@
# Runs tests on one of the simulators
stamps/%/emulator-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
date > $@
stamps/%/emulator-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
date > $@
stamps/%/emulator-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
date > $@
stamps/%/vsim-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
date > $@
stamps/%/vsim-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
date > $@
stamps/%/vsim-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
date > $@
# The torture tests run subtly differently on the different targets, so they

9
src/main/scala/coreplex/Configs.scala
View File

@ -11,19 +11,12 @@ import uncore.devices._
import uncore.converters._
import rocket._
import rocket.Util._
import util.ConfigUtils._
import rocketchip.{GlobalAddrMap, NCoreplexExtClients}
import scala.math.max
import scala.collection.mutable.{LinkedHashSet, ListBuffer}
import DefaultTestSuites._
import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
object ConfigUtils {
def max_int(values: Int*): Int = {
values.reduce((a, b) => max(a, b))
}
}
import ConfigUtils._
class BaseCoreplexConfig extends Config (
topDefinitions = { (pname,site,here) =>
type PF = PartialFunction[Any,Any]

11
src/main/scala/coreplex/Coreplex.scala
View File

@ -57,15 +57,17 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
val debug = new DebugBusIO()(p).flip
val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
val success = Bool(OUTPUT)
val resetVector = UInt(INPUT, p(XLen))
}
def hasSuccessFlag: Boolean = false
val io = new CoreplexIO
}
class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
// Coreplex doesn't know when to stop running
io.success := Bool(false)
// Build a set of Tiles
val tileResets = Wire(Vec(tc.nTiles, Bool()))
val tileList = p(BuildTiles).zip(tileResets).map {
@ -164,8 +166,3 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
io.master.mmio.foreach { _ <> mmioNetwork.port("ext") }
}
}
class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) {
override def hasSuccessFlag = true
io.success.get := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
}

124
src/main/scala/coreplex/TestConfigs.scala → src/main/scala/groundtest/Configs.scala
View File

@ -1,19 +1,133 @@
package coreplex
package groundtest
import Chisel._
import groundtest._
import rocketchip.{GlobalAddrMap}
import rocket._
import uncore.tilelink._
import uncore.coherence._
import uncore.agents._
import uncore.devices.NTiles
import unittest._
import junctions._
import scala.collection.mutable.LinkedHashSet
import scala.collection.immutable.HashMap
import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
import scala.math.max
import ConfigUtils._
import coreplex._
import rocketchip._
import util.ConfigUtils._
/** Actual testing target Configs */
class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
class ComparatorConfig extends Config(
new WithComparator ++ new GroundTestConfig)
class ComparatorL2Config extends Config(
new WithAtomics ++ new WithPrefetches ++
new WithL2Cache ++ new ComparatorConfig)
class ComparatorBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new ComparatorConfig)
class ComparatorStatelessConfig extends Config(
new WithStatelessBridge ++ new ComparatorConfig)
class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
class MemtestL2Config extends Config(
new WithL2Cache ++ new MemtestConfig)
class MemtestBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new MemtestConfig)
class MemtestStatelessConfig extends Config(
new WithNGenerators(0, 1) ++ new WithStatelessBridge ++ new MemtestConfig)
// Test ALL the things
class FancyMemtestConfig extends Config(
new WithNGenerators(1, 2) ++ new WithNCores(2) ++ new WithMemtest ++
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
new WithSplitL2Metadata ++ new WithL2Cache ++ new GroundTestConfig)
class CacheFillTestConfig extends Config(
new WithCacheFillTest ++ new WithPLRU ++ new WithL2Cache ++ new GroundTestConfig)
class BroadcastRegressionTestConfig extends Config(
new WithBroadcastRegressionTest ++ new GroundTestConfig)
class BufferlessRegressionTestConfig extends Config(
new WithBufferlessBroadcastHub ++ new BroadcastRegressionTestConfig)
class CacheRegressionTestConfig extends Config(
new WithCacheRegressionTest ++ new WithL2Cache ++ new GroundTestConfig)
class NastiConverterTestConfig extends Config(new WithNastiConverterTest ++ new GroundTestConfig)
class FancyNastiConverterTestConfig extends Config(
new WithNCores(2) ++ new WithNastiConverterTest ++
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
new WithL2Cache ++ new GroundTestConfig)
class TraceGenConfig extends Config(
new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig)
class TraceGenBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new TraceGenConfig)
class TraceGenL2Config extends Config(
new WithNL2Ways(1) ++ new WithL2Capacity(32 * 64 / 1024) ++
new WithL2Cache ++ new TraceGenConfig)
class MIF128BitComparatorConfig extends Config(
new WithMIFDataBits(128) ++ new ComparatorConfig)
class MIF128BitMemtestConfig extends Config(
new WithMIFDataBits(128) ++ new MemtestConfig)
class MIF32BitComparatorConfig extends Config(
new WithMIFDataBits(32) ++ new ComparatorConfig)
class MIF32BitMemtestConfig extends Config(
new WithMIFDataBits(32) ++ new MemtestConfig)
class PCIeMockupTestConfig extends Config(
new WithPCIeMockupTest ++ new GroundTestConfig)
/* Composable Configs to set individual parameters */
class WithGroundTest extends Config(
(pname, site, here) => pname match {
case BuildCoreplex =>
(p: Parameters, c: CoreplexConfig) => Module(new GroundTestCoreplex(p, c))
case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
TileLinkParameters(
coherencePolicy = (
if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NCoreplexExtClients) + site(NUncachedTileLinkPorts),
maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
site(GroundTestKey).map(_.maxXacts))
.reduce(max(_, _)),
maxClientsPerPort = 1,
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = 8,
dataBits = site(CacheBlockBytes)*8)
}
case BuildTiles => {
val groundtest = if (site(XLen) == 64)
DefaultTestSuites.groundtest64
else
DefaultTestSuites.groundtest32
TestGeneration.addSuite(groundtest("p"))
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
(0 until site(NTiles)).map { i =>
val tileSettings = site(GroundTestKey)(i)
(r: Bool, p: Parameters) => {
Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
case TLId => "L1toL2"
case TileId => i
case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
case NUncachedTileLinkPorts => tileSettings.uncached
})))
}
}
}
case BuildExampleTop =>
(p: Parameters) => uncore.tilelink2.LazyModule(new ExampleTopWithTestRAM(p))
case FPUKey => None
case UseAtomics => false
case UseCompressed => false
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case _ => throw new CDEMatchError
})
class WithComparator extends Config(
(pname, site, here) => pname match {

9
src/main/scala/groundtest/Coreplex.scala Normal file
View File

@ -0,0 +1,9 @@
package groundtest
import Chisel._
import cde.{Parameters}
import coreplex.{CoreplexConfig, DefaultCoreplex}
class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) {
io.success := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
}

7
src/main/scala/groundtest/TestHarness.scala Normal file
View File

@ -0,0 +1,7 @@
package groundtest
import Chisel._
import cde.Parameters
// !!! TODO: Replace with a groundtest-specific test harness
class TestHarness(implicit p: Parameters) extends rocketchip.TestHarness(p)

36
src/main/scala/rocketchip/Top.scala → src/main/scala/rocketchip/BaseTop.scala
View File

@ -53,8 +53,8 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
peripheryBus.node := TLBuffer(TLWidthWidget(TLHintHandler(legacy.node), legacy.tlDataBytes))
}
abstract class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
val success = c.hasSuccessFlag.option(Bool(OUTPUT))
class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
val success = Bool(OUTPUT)
}
abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
@ -63,8 +63,6 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Paramete
val coreplex = p(BuildCoreplex)(p, outer.c)
val io: B = b(coreplex)
io.success zip coreplex.io.success map { case (x, y) => x := y }
val mmioNetwork =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
p.alterPartial({ case TLId => "L2toMMIO" })))
@ -87,32 +85,6 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Paramete
println("Generated Configuration String")
println(p(ConfigString))
ConfigStringOutput.contents = Some(p(ConfigString))
io.success := coreplex.io.success
}
/** Example Top with Periphery */
class ExampleTop(q: Parameters) extends BaseTop(q)
with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryCoreplexLocalInterrupter
with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
}
class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryCoreplexLocalInterrupterBundle
with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryCoreplexLocalInterrupterModule
with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
with HardwiredResetVector
/** Example Top with TestRAM */
class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
with PeripheryTestRAM {
override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
}
class ExampleTopWithTestRAMBundle(p: Parameters, c: Coreplex) extends ExampleTopBundle(p, c)
with PeripheryTestRAMBundle
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: Coreplex => B) extends ExampleTopModule(p, l, b)
with PeripheryTestRAMModule

36
src/main/scala/rocketchip/ExampleTop.scala Normal file
View File

@ -0,0 +1,36 @@
// See LICENSE for license details.
package rocketchip
import Chisel._
import cde.{Parameters, Field}
import coreplex.Coreplex
import rocketchip._
/** Example Top with Periphery */
class ExampleTop(q: Parameters) extends BaseTop(q)
with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryCoreplexLocalInterrupter
with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
}
class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryCoreplexLocalInterrupterBundle
with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryCoreplexLocalInterrupterModule
with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
with HardwiredResetVector
/** Example Top with TestRAM */
class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
with PeripheryTestRAM {
override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
}
class ExampleTopWithTestRAMBundle(p: Parameters, c: Coreplex) extends ExampleTopBundle(p, c)
with PeripheryTestRAMBundle
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: Coreplex => B) extends ExampleTopModule(p, l, b)
with PeripheryTestRAMModule

58
src/main/scala/rocketchip/Generator.scala
View File

@ -8,17 +8,21 @@ import cde._
import coreplex._
import java.io.{File, FileWriter}
/** Representation of the information this Generator needs to collect from external sources. */
case class ParsedInputNames(
targetDir: String,
topProject: String,
topModuleProject: String,
topModuleClass: String,
configProject: String,
configs: String) {
val configClasses: Seq[String] = configs.split('_')
val fullConfigClasses: Seq[String] = configClasses.map(configProject + "." + _)
val fullTopModuleClass: String = topProject + "." + topModuleClass
val fullTopModuleClass: String = topModuleProject + "." + topModuleClass
}
/** Common utilities we supply to all Generators. In particular, supplies the
* canonical ways of building various JVM elaboration-time structures.
*/
trait HasGeneratorUtilities {
def getConfig(names: ParsedInputNames): Config = {
names.fullConfigClasses.foldRight(new Config()) { case (currentName, config) =>
@ -56,40 +60,68 @@ trait HasGeneratorUtilities {
}
}
object ConfigStringOutput {
var contents: Option[String] = None
}
/** Standardized command line interface for Scala entry point */
trait Generator extends App with HasGeneratorUtilities {
lazy val names = {
lazy val names: ParsedInputNames = {
require(args.size == 5, "Usage: sbt> " +
"run TargetDir TopModuleProjectName TopModuleName ConfigProjectName ConfigNameString")
ParsedInputNames(
targetDir = args(0),
topProject = args(1),
topModuleProject = args(1),
topModuleClass = args(2),
configProject = args(3),
configs = args(4))
}
// Canonical ways of building various JVM elaboration-time structures
lazy val td = names.targetDir
lazy val config = getConfig(names)
lazy val world = config.toInstance
lazy val params = Parameters.root(world)
lazy val circuit = elaborate(names, params)
lazy val longName = names.topModuleClass + "." + names.configs
def writeOutputFiles() {
val longName: String // Exhaustive name used to interface with external build tool targets
/** Output FIRRTL, which an external compiler can turn into Verilog. */
def generateFirrtl {
Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
}
/** Output software test Makefrags, which provide targets for integration testing. */
def generateTestSuiteMakefrags {
TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))
writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Coreplex-specific test suites
writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
}
/** Output Design Space Exploration knobs and constraints. */
def generateDSEConstraints {
writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE
writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE
}
/** Output a global Parameter dump, which an external script can turn into Verilog headers. */
def generateParameterDump {
writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
}
/** Output a global ConfigString, for use by the RISC-V software ecosystem. */
def generateConfigString {
ConfigStringOutput.contents.foreach(c => writeOutputFile(td, s"${names.configs}.cfg", c)) // String for software
}
}
object RocketChipGenerator extends Generator {
Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
writeOutputFiles()
object ConfigStringOutput {
var contents: Option[String] = None
}
/** An example Generator */
object RocketChipGenerator extends Generator
{
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateTestSuiteMakefrags
generateDSEConstraints
generateConfigString
generateParameterDump
}

127
src/main/scala/rocketchip/TestConfigs.scala
View File

@ -1,127 +0,0 @@
package rocketchip
import Chisel._
import groundtest._
import rocket._
import uncore.tilelink._
import uncore.coherence._
import uncore.agents._
import uncore.devices.NTiles
import junctions._
import scala.collection.mutable.LinkedHashSet
import scala.collection.immutable.HashMap
import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
import scala.math.max
import coreplex._
import ConfigUtils._
class WithGroundTest extends Config(
(pname, site, here) => pname match {
case BuildCoreplex =>
(p: Parameters, c: CoreplexConfig) => Module(new GroundTestCoreplex(p, c))
case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
TileLinkParameters(
coherencePolicy = (
if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NCoreplexExtClients) + site(NUncachedTileLinkPorts),
maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
site(GroundTestKey).map(_.maxXacts))
.reduce(max(_, _)),
maxClientsPerPort = 1,
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = 8,
dataBits = site(CacheBlockBytes)*8)
}
case BuildTiles => {
val groundtest = if (site(XLen) == 64)
DefaultTestSuites.groundtest64
else
DefaultTestSuites.groundtest32
TestGeneration.addSuite(groundtest("p"))
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
(0 until site(NTiles)).map { i =>
val tileSettings = site(GroundTestKey)(i)
(r: Bool, p: Parameters) => {
Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
case TLId => "L1toL2"
case TileId => i
case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
case NUncachedTileLinkPorts => tileSettings.uncached
})))
}
}
}
case BuildExampleTop =>
(p: Parameters) => uncore.tilelink2.LazyModule(new ExampleTopWithTestRAM(p))
case FPUKey => None
case UseAtomics => false
case UseCompressed => false
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case _ => throw new CDEMatchError
})
class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
class ComparatorConfig extends Config(
new WithComparator ++ new GroundTestConfig)
class ComparatorL2Config extends Config(
new WithAtomics ++ new WithPrefetches ++
new WithL2Cache ++ new ComparatorConfig)
class ComparatorBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new ComparatorConfig)
class ComparatorStatelessConfig extends Config(
new WithStatelessBridge ++ new ComparatorConfig)
class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
class MemtestL2Config extends Config(
new WithL2Cache ++ new MemtestConfig)
class MemtestBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new MemtestConfig)
class MemtestStatelessConfig extends Config(
new WithNGenerators(0, 1) ++ new WithStatelessBridge ++ new MemtestConfig)
// Test ALL the things
class FancyMemtestConfig extends Config(
new WithNGenerators(1, 2) ++ new WithNCores(2) ++ new WithMemtest ++
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
new WithSplitL2Metadata ++ new WithL2Cache ++ new GroundTestConfig)
class CacheFillTestConfig extends Config(
new WithCacheFillTest ++ new WithPLRU ++ new WithL2Cache ++ new GroundTestConfig)
class BroadcastRegressionTestConfig extends Config(
new WithBroadcastRegressionTest ++ new GroundTestConfig)
class BufferlessRegressionTestConfig extends Config(
new WithBufferlessBroadcastHub ++ new BroadcastRegressionTestConfig)
class CacheRegressionTestConfig extends Config(
new WithCacheRegressionTest ++ new WithL2Cache ++ new GroundTestConfig)
class NastiConverterTestConfig extends Config(new WithNastiConverterTest ++ new GroundTestConfig)
class FancyNastiConverterTestConfig extends Config(
new WithNCores(2) ++ new WithNastiConverterTest ++
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
new WithL2Cache ++ new GroundTestConfig)
class TraceGenConfig extends Config(
new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig)
class TraceGenBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new TraceGenConfig)
class TraceGenL2Config extends Config(
new WithNL2Ways(1) ++ new WithL2Capacity(32 * 64 / 1024) ++
new WithL2Cache ++ new TraceGenConfig)
class MIF128BitComparatorConfig extends Config(
new WithMIFDataBits(128) ++ new ComparatorConfig)
class MIF128BitMemtestConfig extends Config(
new WithMIFDataBits(128) ++ new MemtestConfig)
class MIF32BitComparatorConfig extends Config(
new WithMIFDataBits(32) ++ new ComparatorConfig)
class MIF32BitMemtestConfig extends Config(
new WithMIFDataBits(32) ++ new MemtestConfig)
class PCIeMockupTestConfig extends Config(
new WithPCIeMockupTest ++ new GroundTestConfig)

25
src/main/scala/rocketchip/TestHarness.scala
View File

@ -5,6 +5,7 @@ package rocketchip
import Chisel._
import cde.{Parameters, Field}
import rocket.Util._
import util.LatencyPipe
import junctions._
import junctions.NastiConstants._
@ -137,12 +138,12 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
}
def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.DebugBusIO,
dutsuccess: Option[Bool], tbsuccess: Bool) = {
dutsuccess: Bool, tbsuccess: Bool) = {
io.clk := tbclk
io.reset := tbreset
dutio <> io.debug
tbsuccess := dutsuccess.getOrElse(io.exit === 1)
tbsuccess := dutsuccess || io.exit === 1
when (io.exit >= 2) {
printf("*** FAILED *** (exit code = %d)\n", io.exit >> 1)
stop(1)
@ -176,23 +177,3 @@ class JTAGVPI(implicit val p: Parameters) extends BlackBox {
tbsuccess := Bool(false)
}
}
class LatencyPipe[T <: Data](typ: T, latency: Int) extends Module {
val io = new Bundle {
val in = Decoupled(typ).flip
val out = Decoupled(typ)
}
def doN[T](n: Int, func: T => T, in: T): T =
(0 until n).foldLeft(in)((last, _) => func(last))
io.out <> doN(latency, (last: DecoupledIO[T]) => Queue(last, 1, pipe=true), io.in)
}
object LatencyPipe {
def apply[T <: Data](in: DecoupledIO[T], latency: Int): DecoupledIO[T] = {
val pipe = Module(new LatencyPipe(in.bits, latency))
pipe.io.in <> in
pipe.io.out
}
}

46
src/main/scala/rocketchip/UnitTest.scala
View File

@ -1,46 +0,0 @@
// See LICENSE for license details.
package rocketchip
import scala.collection.mutable.LinkedHashSet
import Chisel._
import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
import util.{ParameterizedBundle}
import rocket._
import uncore.tilelink._
import uncore.tilelink2.{LazyModule, LazyModuleImp}
import coreplex._
import rocketchip._
import unittest._
class WithUnitTest extends Config(
(pname, site, here) => pname match {
case UnitTests => (testParams: Parameters) => {
val groundtest = if (site(XLen) == 64)
DefaultTestSuites.groundtest64
else
DefaultTestSuites.groundtest32
TestGeneration.addSuite(groundtest("p"))
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
}
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case _ => throw new CDEMatchError
})
class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
class UnitTestHarness(implicit val p: Parameters) extends Module {
val io = new Bundle {
val success = Bool(OUTPUT)
}
val l1params = p.alterPartial({
case NCoreplexExtClients => 0
case ConfigString => ""
case TLId => "L1toL2" })
val tests = Module(new UnitTestSuite()(l1params))
io.success := tests.io.finished
}

44
src/main/scala/unittest/Configs.scala Normal file
View File

@ -0,0 +1,44 @@
// See LICENSE for license details.
package unittest
import scala.collection.mutable.LinkedHashSet
import Chisel._
import cde.{Parameters, Config, CDEMatchError}
import coreplex._
import rocketchip._
class WithJunctionsUnitTests extends Config(
(pname, site, here) => pname match {
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case UnitTests => (p: Parameters) => {
TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
Seq(
Module(new junctions.MultiWidthFifoTest),
Module(new junctions.NastiMemoryDemuxTest()(p)),
Module(new junctions.HastiTest()(p)))
}
case UnitTestTimeout => 50000
case _ => throw new CDEMatchError
})
class WithUncoreUnitTests extends Config(
(pname, site, here) => pname match {
case NCoreplexExtClients => 0
case uncore.tilelink.TLId => "L1toL2"
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case UnitTests => (p: Parameters) => {
TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
Seq(
Module(new uncore.devices.ROMSlaveTest()(p)),
Module(new uncore.devices.TileLinkRAMTest()(p)),
Module(new uncore.tilelink2.TLFuzzRAMTest))
}
case UnitTestTimeout => 500000
case _ => throw new CDEMatchError
})
class UnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithJunctionsUnitTests ++ new BaseConfig)

20
src/main/scala/unittest/TempListOfTests.scala
View File

@ -1,20 +0,0 @@
package unittest
import Chisel._
import cde.Parameters
object JunctionsUnitTests {
def apply(implicit p: Parameters): Seq[UnitTest] =
Seq(
Module(new junctions.MultiWidthFifoTest),
Module(new junctions.NastiMemoryDemuxTest),
Module(new junctions.HastiTest))
}
object UncoreUnitTests {
def apply(implicit p: Parameters): Seq[UnitTest] =
Seq(
Module(new uncore.devices.ROMSlaveTest),
Module(new uncore.devices.TileLinkRAMTest),
Module(new uncore.tilelink2.TLFuzzRAMTest))
}

10
src/main/scala/unittest/TestHarness.scala Normal file
View File

@ -0,0 +1,10 @@
// See LICENSE for license details.
package unittest
import Chisel._
class TestHarness(implicit val p: cde.Parameters) extends Module {
val io = new Bundle { val success = Bool(OUTPUT) }
io.success := Module(new UnitTestSuite).io.finished
}

3
src/main/scala/unittest/UnitTest.scala
View File

@ -18,6 +18,7 @@ abstract class UnitTest extends Module with HasUnitTestIO {
}
case object UnitTests extends Field[Parameters => Seq[UnitTest]]
case object UnitTestTimeout extends Field[Int]
class UnitTestSuite(implicit p: Parameters) extends Module {
val io = new Bundle {
@ -39,7 +40,7 @@ class UnitTestSuite(implicit p: Parameters) extends Module {
state := Mux(test_idx === UInt(tests.size - 1), s_done, s_start)
}
val timer = Module(new Timer(500000, tests.size))
val timer = Module(new Timer(p(UnitTestTimeout), tests.size))
timer.io.start.valid := Bool(false)
timer.io.stop.valid := Bool(false)

11
src/main/scala/util/ConfigUtils.scala Normal file
View File

@ -0,0 +1,11 @@
// See LICENSE for license details.
package util
import scala.math.max
object ConfigUtils {
def max_int(values: Int*): Int = {
values.reduce((a, b) => max(a, b))
}
}

25
src/main/scala/util/LatencyPipe.scala Normal file
View File

@ -0,0 +1,25 @@
// See LICENSE for license details.
package util
import Chisel._
class LatencyPipe[T <: Data](typ: T, latency: Int) extends Module {
val io = new Bundle {
val in = Decoupled(typ).flip
val out = Decoupled(typ)
}
def doN[T](n: Int, func: T => T, in: T): T =
(0 until n).foldLeft(in)((last, _) => func(last))
io.out <> doN(latency, (last: DecoupledIO[T]) => Queue(last, 1, pipe=true), io.in)
}
object LatencyPipe {
def apply[T <: Data](in: DecoupledIO[T], latency: Int): DecoupledIO[T] = {
val pipe = Module(new LatencyPipe(in.bits, latency))
pipe.io.in <> in
pipe.io.out
}
}

3
vsim/Makefile
View File

@ -17,13 +17,12 @@ sim_dir = .
output_dir = $(sim_dir)/output
BACKEND ?= v
CONFIG ?= DefaultConfig
TB ?= TestDriver
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(generated_dir)/$(MODEL).$(CONFIG).d
-include $(generated_dir)/$(long_name).d
endif
include $(base_dir)/vsim/Makefrag-verilog

9
vsim/Makefrag
View File

@ -15,8 +15,8 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
sim_vsrcs = \
$(generated_dir)/$(MODEL).$(CONFIG).v \
$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v \
$(generated_dir)/$(long_name).v \
$(generated_dir)/$(long_name).behav_srams.v \
$(generated_dir)/consts.$(CONFIG).vh \
$(base_dir)/vsrc/$(TB).v \
$(base_dir)/vsrc/SimDTM.v \
@ -52,7 +52,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
$(RISCV)/lib/libfesvr.so \
-sverilog \
+incdir+$(generated_dir) \
+define+MODEL=$(MODEL) \
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \
@ -71,14 +70,14 @@ VCS_OPTS += -CC "-DVCS_VPI"
# Build the simulator
#--------------------------------------------------------------------
simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
$(simv) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
cd $(sim_dir) && \
rm -rf csrc && \
$(VCS) $(VCS_OPTS) -o $(simv) \
-debug_pp \
simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
cd $(sim_dir) && \
rm -rf csrc && \

23
vsim/Makefrag-verilog
View File

@ -1,29 +1,28 @@
#--------------------------------------------------------------------
# Verilog Generation
#--------------------------------------------------------------------
firrtl = $(generated_dir)/$(long_name).fir
verilog = $(generated_dir)/$(long_name).v
# If I don't mark these as .SECONDARY then make will delete these internal
# files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
.SECONDARY: $(firrtl) $(verilog)
firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir
.PHONY: firrtl
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_JAR)
$(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
mkdir -p $(dir $@)
$(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf
$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen)
$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
cd $(generated_dir) && \
rm -f $@ && \
$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $@.tmp && \
$(mem_gen) $(generated_dir)/$(long_name).conf >> $@.tmp && \
mv $@.tmp $@
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(long_name).prm
echo "\`ifndef CONST_VH" > $@
echo "\`define CONST_VH" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@

2
vsrc/TestDriver.v
View File

@ -87,7 +87,7 @@ module TestDriver;
end
end
`MODEL testHarness(
TestHarness testHarness(
.clk(clk),
.reset(reset),
.io_success(success)