Henry Cook
d3ccec1044
Massive update containing several months of changes from the now-defunct private chip repo.
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* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
Henry Cook
d7cb60e8fa
L2 WritebackUnit bug fix
2015-07-02 13:52:40 -07:00
Scott Beamer
12d8d8c5e3
Merge pull request #8 from seldridge/master
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Fix FPGA/VLSI Mem Gen for Python 2 and 3 Environments
2015-06-28 08:54:24 -05:00
Schuyler Eldridge
b4cd8c5981
Fix vlsi_mem_gen for Python 2 or 3
2015-06-25 12:48:31 -07:00
Schuyler Eldridge
a42832fc70
Fix fpga_mem_gen for Python 2 and 3 Environments
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Two quick fixes that enable fpga_mem_gen to work with either Python 2 or
Python 3:
* Change an `xrange` instance to `range`
* Wrap the arguments of a bare `print` in parentheses
2015-06-25 11:03:33 -07:00
Andrew Waterman
b4e38192a1
Fix (?) L2$ miss bug
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The victim's metadata was incorrectly used for the new line.
2015-06-24 18:01:56 -07:00
Andrew Waterman
5e009ecc75
Fix an apparently benign PC sign-extension bug
2015-06-11 16:08:39 -07:00
Andrew Waterman
ea76800d1a
Fix data array reset bug
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io.resp.valid could have been valid the cycle after reset, causing the
write mask in the acquire tracker to have an erroneous value after reset.
This caused the L1 I$ to be refilled with the wrong data.
This probably only affects programs loaded with +loadmem and so shouldn't
matter for the EOS24 silicon. It should only affect the first L2 xact,
which, in practice, would be an HTIF write to load the program.
2015-06-11 15:28:23 -07:00
Colin Schmidt
4b6cd7f3eb
Merge branch 'master' of ucb-bar/rocket into rocc-fpu-port for priv1.7
2015-06-03 15:51:53 -07:00
Wei Song
4db60d9e9d
code clean in dcache, no need to check the condition twice.
2015-06-02 22:06:12 +01:00
Wei Song
b6e68773fd
nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array.
2015-05-30 16:25:27 +01:00
Henry Cook
f3a838cedf
nasti converters, hub bugfix
2015-05-21 19:49:17 -07:00
Scott Beamer
a59ba39310
bump submodule for fpga-zynq
2015-05-21 11:26:57 -07:00
Scott Beamer
38edbc78e5
Merge pull request #5 from amsharifian/master
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Update Makefile
2015-05-21 11:24:25 -07:00
Andrew Waterman
6a9390c50e
Avoid spurious D$ assertion failures
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For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
2015-05-19 03:00:53 -07:00
Andrew Waterman
f460cb6c54
Update to privileged architecture 1.7
2015-05-19 02:32:21 -07:00
Andrew Waterman
254498042a
Fix Split for 0-width wires
2015-05-18 18:23:17 -07:00
Andrew Waterman
d31b26c342
Clean up handling of icache's io.cpu.npc signal
2015-05-18 18:22:48 -07:00
Henry Cook
c202449e34
first version NASTI IOs
2015-05-14 15:29:49 -07:00
Henry Cook
90c9ee7b04
fix unalloc putblocks
2015-05-14 12:37:35 -07:00
Henry Cook
a7fa77c7fc
track operand size for Gets
2015-05-13 23:28:18 -07:00
Henry Cook
172c372d3e
L2 alloc cleanup
2015-05-12 17:14:06 -07:00
Henry Cook
5fdae2cb61
Merge branch 'master' of github.com:ucb-bar/uncore
2015-05-07 16:18:23 -07:00
Henry Cook
fc883b5049
rm index.html
2015-05-07 16:17:40 -07:00
Henry Cook
8362eba00f
Merge branch 'gh-pages'
2015-05-07 16:16:13 -07:00
Henry Cook
aec24cf1a7
readme
2015-05-07 16:16:07 -07:00
Henry Cook
62b6f24798
Delete TileLink0.3.1Specification.pdf
2015-05-07 15:43:06 -07:00
Henry Cook
90ced93eeb
Merge branch 'master' into gh-pages
2015-05-07 12:35:14 -07:00
Henry Cook
4cef8c9cd4
Added MemIOArbiter
2015-05-07 10:55:38 -07:00
Christopher Celio
b09832f1b5
ICache now returns the "next PC" signal.
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useful for other modules that need access to the fetch PC on the
cycle it is sent to the SRAM.
2015-05-07 04:53:05 -07:00
Colin Schmidt
c746ef8702
fix bug in rocc port resp for FPtoInt instructions
2015-05-04 11:20:55 -07:00
Henry Cook
8832b454ce
add plugins to make scala doc site and publish to ghpages
2015-04-29 15:34:56 -07:00
Henry Cook
1e05fc0525
First pages commit
2015-04-29 13:18:26 -07:00
Yunsup Lee
b9fb1bb46e
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-04-29 00:43:53 -07:00
Henry Cook
3673295d03
network shim cleanup
2015-04-27 16:59:30 -07:00
Henry Cook
09e30041ed
Voluntary Writeback tracker rewrite
2015-04-27 12:56:33 -07:00
Colin Schmidt
a37fad2e9b
Merge branch 'retimeable-frontend' into rocc-fpu-port
2015-04-22 14:23:52 -07:00
Colin Schmidt
1f410ac42c
move fetch buffer into frontend to allow retiming
2015-04-22 11:26:03 -07:00
Henry Cook
11b5222d01
Refactored WritebackUnit
2015-04-21 22:23:04 -07:00
Henry Cook
4c7969b2b3
Metadata docs and api cleanup
2015-04-20 16:32:09 -07:00
Henry Cook
a315fe93c1
simplify ClientMetadata.makeRelease
2015-04-20 10:46:24 -07:00
Henry Cook
f66a9fd7a6
simplify ClientMetadata.makeRelease
2015-04-20 10:46:02 -07:00
Henry Cook
6d40a61060
TileLink scala doc and parameter renaming
2015-04-19 22:06:44 -07:00
Albert Ou
ca5b3d988d
Merge branch 'master' into rocc-fpu-port
2015-04-19 15:00:00 -07:00
Henry Cook
3048f4785a
HeaderlessTileLinkIO -> ClientTileLinkIO
2015-04-17 16:56:53 -07:00
Henry Cook
ba7a8b1752
TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R).
2015-04-17 16:55:20 -07:00
Colin Schmidt
73fa28521d
Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port
2015-04-16 15:22:08 -07:00
Henry Cook
ce3271aef2
refactor LNClients and LNManagers
2015-04-15 15:48:36 -07:00
Henry Cook
49f1c0aa7b
moved ecc lib to uncore
2015-04-13 15:58:10 -07:00
Henry Cook
91e882e3f8
Use HeaderlessTileLinkIO
2015-04-13 15:58:10 -07:00
