Henry Cook
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ebdc0a2692
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merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
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2014-04-10 12:09:52 -07:00 |
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Henry Cook
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2c2b3a7678
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cleanups supporting uncore hierarchy
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2014-01-31 12:07:26 -08:00 |
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Andrew Waterman
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57f4d89c90
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Generate D$ replay_next signals correctly
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2014-01-16 00:16:09 -08:00 |
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Andrew Waterman
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6ebdc4d94e
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Simplify store conditional failure code generation
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2014-01-16 00:15:48 -08:00 |
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Andrew Waterman
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31060ea8ae
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Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working. Hopefully this does it.
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2014-01-14 04:02:43 -08:00 |
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Andrew Waterman
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e8486817e6
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Clean up formatting (i.e. remove tabs, semicolons)
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2014-01-13 21:43:56 -08:00 |
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Andrew Waterman
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07a91bb99a
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Miscellaneous cleanup
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2013-12-09 19:53:14 -08:00 |
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Andrew Waterman
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924261e2b2
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Update to new privileged ISA... phew
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2013-11-25 04:35:15 -08:00 |
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Yunsup Lee
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1583560757
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fix replay bug, don't respond when cmd is a NOP
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2013-10-28 22:35:18 -07:00 |
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Andrew Waterman
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f12bbc1e43
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working RoCC AccumulatorExample
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2013-09-14 22:34:53 -07:00 |
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Andrew Waterman
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18968dfbc7
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Move store data generation into cache
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2013-09-14 16:15:07 -07:00 |
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Andrew Waterman
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d053bdc89f
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Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
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2013-09-12 22:34:38 -07:00 |
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Andrew Waterman
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59f5358435
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Implement AQ/RL; move fence logic out of cache
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2013-09-12 16:07:30 -07:00 |
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Henry Cook
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f9b85d8158
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NetworkIOs no longer use thunks
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2013-09-10 16:15:19 -07:00 |
|
Henry Cook
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d06e24ac24
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new enum syntax
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2013-09-10 10:51:35 -07:00 |
|
Henry Cook
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
|
Henry Cook
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
|
Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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Henry Cook
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
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Henry Cook
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bef6c1db35
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minor nbdcache cleanup
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2013-08-02 16:29:37 -07:00 |
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Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Henry Cook
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569d8fd796
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Merge branch 'tilelink-data'
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2013-05-23 14:14:40 -07:00 |
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Henry Cook
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69b508ff39
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ported caches and htif to use new tilelink
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2013-05-21 17:21:04 -07:00 |
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Andrew Waterman
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1dab984231
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use UFix instead of Bits for arithmetic
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2013-05-18 00:45:29 -07:00 |
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Andrew Waterman
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474d321cc7
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fix meta hazard counter to reset on new meta writes
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2013-05-01 16:35:24 -07:00 |
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Andrew Waterman
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a6a88fce19
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Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
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2013-05-01 16:34:45 -07:00 |
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Andrew Waterman
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63a38e7982
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Revert "temp"
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
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2013-05-01 16:34:33 -07:00 |
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Henry Cook
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b6945408cb
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temp
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2013-05-01 10:24:36 -07:00 |
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Henry Cook
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722bc917d3
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broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle
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2013-05-01 10:05:54 -07:00 |
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Andrew Waterman
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1501e90c1f
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interlock probe unit on tag RAW hazards
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2013-04-30 00:38:22 -07:00 |
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Henry Cook
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e8b20f3d38
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clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant
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2013-04-25 17:41:04 -07:00 |
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Andrew Waterman
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ae7720e284
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guarantee LR/SC forward progress
the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
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2013-04-07 19:27:21 -07:00 |
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Andrew Waterman
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e74e032c87
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simplify MSHR memory response logic
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2013-04-06 01:03:37 -07:00 |
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Andrew Waterman
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1abb9277db
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fix LR/SC atomicity violation
note, it's still not starvation-free.
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2013-04-05 19:13:38 -07:00 |
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Andrew Waterman
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8cbdeb2abf
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add LR/SC support
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2013-04-04 17:07:09 -07:00 |
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Henry Cook
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f8aebcbf8c
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fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
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2013-04-04 15:50:29 -07:00 |
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Henry Cook
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95f0a688e9
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Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
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2013-03-20 17:37:50 -07:00 |
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Henry Cook
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273bd34091
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Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
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2013-03-20 15:53:36 -07:00 |
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Andrew Waterman
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ea9d0b771e
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remove aborts; simplify probes
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2013-03-19 15:29:40 -07:00 |
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Henry Cook
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e0361840bd
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writebacks on release network pass asm tests and bmarks
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2013-02-28 18:11:40 -08:00 |
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Andrew Waterman
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35349d227f
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update to new Mem style
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2013-02-20 16:09:46 -08:00 |
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Andrew Waterman
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1fbc20450e
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don't allow simultaneous reads and writes to the tag ram
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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37ee843b2c
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don't use reset combinationally
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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bb6fbddf1f
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don't probe the mshr file to inquire about refills
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2013-01-24 17:54:59 -08:00 |
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Rimas Avizienis
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63060bc0a8
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minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
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2013-01-23 19:27:53 -08:00 |
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Henry Cook
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6b00e7ff74
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New TileLink bundle names
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2013-01-21 17:18:23 -08:00 |
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Henry Cook
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a2fa3fd04d
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Refactored packet headers/payloads
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2013-01-15 15:50:37 -08:00 |
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Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Henry Cook
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261e14f831
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Refactored uncore conf
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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f5c53ce35d
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add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
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2012-12-11 15:58:53 -08:00 |
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