Howard Mao
dcfcac9530
fix LRSC issue (RocketChip issue #86 )
...
It was possible that the result of a store-conditional could get lost if it
did not depend on the result of the corresponding load-reserved.
This was because the MSHR does not update the client state based on the
secondary requests. So the LR would acquire the line in clientExcusiveClean,
but then we would fail to update the metadata array to change the state
to clientExclusiveDirty.
The solution is to track whether a secondary acquire would cause the
line to be dirty. If so, use M_XWR instead of the primary command to
generate the update coherence state.
2016-07-26 18:41:52 -07:00
Howard Mao
51edd19e85
add U bit to misa register
2016-07-22 14:22:59 -07:00
Howard Mao
2723b2f515
fix issues in SimpleHellaCacheIF and document the changes
2016-07-18 17:02:47 -07:00
Howard Mao
40a146f625
HellaCacheArbiter passes through if n == 1
2016-07-18 17:01:29 -07:00
Howard Mao
f7b392306e
make sure SimpleHellaCacheIF can work with blocking DCache
2016-07-07 18:59:23 -07:00
Howard Mao
a9e0a5e2df
changes to imports after uncore refactor
2016-06-28 14:09:31 -07:00
Howard Mao
4c31248917
make sure UseAtomics is on when PTW is being used
2016-06-22 16:09:45 -07:00
Howard Mao
d1c83ccda0
change Tile interface to allow arbitrary number of cached and uncached channels
2016-06-20 09:55:30 -07:00
Howard Mao
f228309bd1
add assertion to make sure SimpleHellaCacheIF doesn't get exception
2016-05-20 16:30:27 -07:00
Howard Mao
5cbcc41515
get rid of unused imports
2016-05-02 18:23:46 -07:00
Howard Mao and Andrew Waterman
b7527268bb
use address map instead of MMIOBase to find size of memory
2016-04-21 18:44:39 -07:00
Howard Mao
5abfd1a4ab
make sure to check for region violations in DMA frontend
2016-02-03 15:40:44 -08:00
Howard Mao
78579672d3
make mtvec configurable and writeable
2016-01-29 14:51:56 -08:00
Howard Mao
7937fbf074
fix number of IOMSHRs at 1
2016-01-29 14:51:56 -08:00
Howard Mao
305185c034
send DMA requests through MMIO and get responses through CSRs
2016-01-29 14:51:56 -08:00
Howard Mao
d170fcd913
DecoupledHelper is now imported from junctions
2016-01-21 15:38:43 -08:00
Howard Mao
77e068c153
fix Chisel3 compat issue in SimpleHellaCacheIF
2016-01-14 22:42:44 -08:00
Howard Mao
120361226d
fix more Chisel3 deprecations
2016-01-14 14:46:31 -08:00
Howard Mao
d51c127646
fix deprecation warnings in rocket.scala
2016-01-13 22:08:06 -08:00
Howard Mao
13ce91e453
fix Chisel3 compat warnings in ICache and FPU
2016-01-12 12:43:48 -08:00
Howard Mao
05b359d357
support streaming DMA in DMA frontend
2016-01-06 18:17:41 -08:00
Howard Mao
dbe68056d9
Merge pull request #21 from ucb-bar/dma
...
Implement client-side DMA controller
2015-12-22 10:33:28 -05:00
Howard Mao
304d8b814a
Implement client-side DMA controller
2015-12-16 21:24:24 -08:00
Howard Mao
7690de07e1
allow icache to configure which side of the way mux gets buffered
2015-12-02 17:17:49 -08:00
Howard Mao
369ee74a2c
change names of RoCC tilelink interfaces to be more sensible
2015-12-02 16:28:23 -08:00
Howard Mao
f67b02fadb
Merge branch 'rocc-fpu-port'
2015-12-02 08:52:15 -08:00
Howard Mao
73b0263663
disconnect fpu port if no fpu-using RoCC accelerators
2015-12-01 20:41:58 -08:00
Howard Mao
3f8f726296
make rocc build independent from parameter structure
2015-12-01 18:47:52 -08:00
Howard Mao
dcca0b1d86
fix up FPU connection
2015-12-01 18:14:58 -08:00
Howard Mao
08f77ca90d
Merge branch 'master' into rocc-fpu-port
2015-12-01 18:00:28 -08:00
Howard Mao
e76dfa55f7
change the way rocc is parameterized
2015-12-01 17:54:56 -08:00
Howard Mao
4833d41dbc
make the connection of FPU ports optional per accelerator
2015-12-01 16:48:05 -08:00
Howard Mao
0b15b19381
add arbiter for FPU
2015-12-01 10:22:31 -08:00
Howard Mao
1db2da00f3
Merge branch 'master' into rocc-fpu-port
2015-11-30 19:18:58 -08:00
Howard Mao
e80340198a
use implicit parameters for ALU
2015-11-30 17:35:33 -08:00
Howard Mao
9256239206
implement support for multiple RoCC accelerators
2015-11-26 12:46:01 -08:00
Howard Mao
58b0a86834
some modifications to AccumulatorExample
2015-11-26 08:48:19 -08:00
Howard Mao
b0a06a77db
fix a few Chisel3 compat issues
2015-11-20 13:33:15 -08:00
Howard Mao
19daee10f0
use default constructors for IOMSHR acquire construction
2015-11-12 15:54:05 -08:00
Howard Mao
0b7c828b5d
go back to using standard LockingArbiter
2015-10-21 09:15:51 -07:00
Howard Mao
c68d9f8137
make ProbeUnit state machine easier to understand
2015-10-20 23:25:23 -07:00
Howard Mao
19656e4abe
make sure to generate release from clean coh state on probe miss
2015-09-30 16:58:18 -07:00
Howard Mao
2f3d15675c
fix DataArray writemask in L1D
2015-09-28 16:02:39 -07:00
Howard Mao
4bda6b6757
fix bug in tlb refill
2015-09-26 21:27:36 -07:00
Howard Mao
6bf8f41cef
make sure passthrough requests are treated as vm_enabled = false
2015-09-26 20:29:51 -07:00
Howard Mao
a66bdb1956
replace remaining uses of Vec.fill
2015-09-24 17:53:26 -07:00
Howard Mao
9eb988a4c6
make sure access to invalid physical address treated as exception
2015-09-22 10:11:43 -07:00
Howard Mao
16c748576a
don't mux data_word_bypass between IOMSHR and cache
2015-09-22 10:10:57 -07:00
Howard Mao
d89bcd3922
modify csr file to bring in line with HTIF changes
2015-09-22 10:10:57 -07:00
Howard Mao
382faba4a6
Implement bypassing L1 data cache for MMIO
2015-09-22 10:10:57 -07:00
Howard Mao
