d78f1aacd0
Clean up some zero-width wire cases using UInt.extract
2016-07-14 22:08:01 -07:00
da512d4230
Explicitly discard BTB index LSBs
2016-07-14 17:10:27 -07:00
e6aab368a4
Replace ICacheBufferWays parameter with I$ constructor argument
2016-07-14 12:38:54 -07:00
3d0b92afd7
Misc code cleanup
2016-07-14 12:09:34 -07:00
b8884e8143
Simplify frontend virtual address extension code
2016-07-14 12:05:09 -07:00
1699622730
Don't speculatively refill I$ in uncacheable regions
2016-07-09 01:10:58 -07:00
f7b392306e
make sure SimpleHellaCacheIF can work with blocking DCache
2016-07-07 18:59:23 -07:00
3d8939d3c3
Set misa.base = 1 for RV32
2016-07-07 15:32:21 -07:00
2455a806af
Make WFI instruction respect mie CSR setting
2016-07-07 15:31:17 -07:00
35a983275e
Guarantee one-hotness of BTB entries
2016-07-06 15:58:01 -07:00
c0e6ecebfc
Fix BTB perf bug
...
In rare cases, it would replace into a different row than it recorded.
2016-07-06 03:16:05 -07:00
f3e22984d5
Remove uarch counters
...
These will be replaced with the indirect TDR scheme used by breakpoints.
2016-07-06 01:41:41 -07:00
25fdabdd59
Don't implicitly create Vecs, since they're heavyweight
2016-07-06 01:41:31 -07:00
8bd7e3932b
Implement priv-1.9 PTE scheme
2016-07-05 19:19:49 -07:00
ebefe57036
simplify BTB fetchWidth=1 special case
2016-07-04 23:43:47 -07:00
2d325df60c
Improve PTW simulation performance
2016-07-02 14:34:18 -07:00
5aa8ef1855
Remove invalidation support from BTB
...
Validating the target PC in the pipeline is cheaper than maintaining
the valid bits and control logic to guarantee the BTB won't ever
mispredict branch targets.
2016-07-02 14:27:29 -07:00
663002ec0c
Improve TLB simulation performance
2016-07-02 14:26:05 -07:00
a9e0a5e2df
changes to imports after uncore refactor
2016-06-28 14:09:31 -07:00
c10691b616
Don't take interrupts on instructions in branch shadow
...
In situations like
j 1f
nop
1: nop
the interrupt could be taken on the first nop.
2016-06-28 12:47:49 -07:00
a70dee17ea
Make RoCC energy-saving logic mirror same for D$
2016-06-28 12:47:45 -07:00
6f85056494
Remove reliance on HtifKey
2016-06-23 13:18:51 -07:00
6d43c0a945
Mask interrupts during single-step
2016-06-23 00:01:06 -07:00
5644a2703a
Avoid need for FENCE.I in debug programs
...
This is a hack to work around caching the (uncacheable) debug RAM. The
RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR.
2016-06-23 00:01:06 -07:00
7f88a00a38
Always verify BTB result; don't bother flushing it
...
This improves CPI for things like
lbu t0, (t0)
j foo
addi t0, t0, 1
where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
2016-06-23 00:01:06 -07:00
4c31248917
make sure UseAtomics is on when PTW is being used
2016-06-22 16:09:45 -07:00
d1c83ccda0
change Tile interface to allow arbitrary number of cached and uncached channels
2016-06-20 09:55:30 -07:00
60bddddfe6
Merge sptbr and sasid
2016-06-17 18:29:05 -07:00
0b4c8e9af7
Add D-mode single-step support
2016-06-15 16:21:24 -07:00
e3816d5fc7
set invalidate_lr in other rocc examples ( #47 )
...
This should fix https://travis-ci.org/ucb-bar/rocket-chip/jobs/137607305
2016-06-14 16:59:37 -07:00
e3b4b55836
Refactor breakpoints and support range comparison (currently disabled)
2016-06-10 19:55:58 -07:00
c8c7246cce
Update breakpoint spec
2016-06-09 19:07:21 -07:00
2c325151bf
pass invalidate_lr through simple cache interface ( #45 )
2016-06-09 17:22:36 -07:00
586c1079d0
Fix D$ for set size > page size
2016-06-09 13:02:28 -07:00
dca55a2b35
Respect breakpoint privilege settings
2016-06-09 12:41:52 -07:00
c85ea7b987
Set badaddr on breakpoints
2016-06-09 12:33:43 -07:00
4cd77cef10
Make dcsr.halt writable
2016-06-09 12:30:09 -07:00
8516e38eb2
remove implicit modulo addressing in FPU ( #44 )
2016-06-09 11:33:33 -07:00
e3c17b5f74
Add provisional breakpoint support
2016-06-08 20:19:52 -07:00
4f2e2480a8
When exceptions occur in D-mode, set pc=0x808, not 0x800
...
Closes #43
2016-06-06 20:57:22 -07:00
3b0c1ed0c3
Cope with changes to AddrMap
2016-06-03 13:50:29 -07:00
13386af1d1
Get rid of unused implicit conversion
2016-06-01 19:30:41 -07:00
9949347569
First stab at debug interrupts
2016-06-01 16:57:10 -07:00
51379621d6
Flush blocking D$ on FENCE.I
2016-05-31 19:27:28 -07:00
3ee5144923
Fix TLB tag check logic when ASIDs are present
2016-05-27 12:24:17 -07:00
c104b57c52
Use BitPat implicit conversion in instruction decoder
2016-05-26 22:23:21 -07:00
96fa1eb6ad
Add UInt->BitPat implicit conversion
...
This will be removed from Chisel3, so we're putting it here to maintain
compatibility.
2016-05-26 18:52:53 -07:00
0c50bfcfb3
Work around more zero-width wire cases
2016-05-25 21:47:48 -07:00
40f38dde63
Work around lack of zero-width wires in D$
2016-05-25 19:44:31 -07:00
00ea9a7d82
Remove most of mstatus when user mode isn't supported
2016-05-25 15:37:32 -07:00
