Andrew Waterman
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1edb1e2a0a
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Ignore LSB of PC
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2013-09-12 17:55:58 -07:00 |
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Andrew Waterman
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59f5358435
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Implement AQ/RL; move fence logic out of cache
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2013-09-12 16:07:30 -07:00 |
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Andrew Waterman
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243c4ae342
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sync up rocket with new isa
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2013-09-12 03:44:38 -07:00 |
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Andrew Waterman
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95dd0d8be1
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Remove DebugIO/error mode
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2013-09-11 20:15:21 -07:00 |
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Henry Cook
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f9b85d8158
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NetworkIOs no longer use thunks
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2013-09-10 16:15:19 -07:00 |
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Henry Cook
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d06e24ac24
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new enum syntax
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2013-09-10 10:51:35 -07:00 |
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Stephen Twigg
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cfbfa6b895
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Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
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2013-09-05 19:22:34 -07:00 |
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Stephen Twigg
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d896ccbd43
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
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2013-09-05 16:11:53 -07:00 |
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Andrew Waterman
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b9f6e1a7ec
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Don't update BTB when garbage was fetched
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2013-08-26 14:53:04 -07:00 |
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Yunsup Lee
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44e92edf92
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fix scr parameterization bug
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2013-08-24 22:42:51 -07:00 |
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Andrew Waterman
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3895b75a56
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Support non-power-of-2 BTBs; prefer invalid entries
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2013-08-24 17:33:11 -07:00 |
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Yunsup Lee
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2ca5127785
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parameterize number of SCRs
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2013-08-24 15:47:14 -07:00 |
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Andrew Waterman
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daf23b8f79
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Add early out to multiplier
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2013-08-24 14:44:23 -07:00 |
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Andrew Waterman
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67f80ba4b2
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Stall div/mul writeback until WB slot is free
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2013-08-24 14:44:17 -07:00 |
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Andrew Waterman
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d1b5076fee
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Don't update BTB when garbage was fetched
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2013-08-24 14:44:11 -07:00 |
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Andrew Waterman
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52e31f3298
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Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
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2013-08-24 14:44:04 -07:00 |
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Andrew Waterman
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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Henry Cook
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ff7b486006
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standardized sbt build
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2013-08-15 18:13:19 -07:00 |
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Henry Cook
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ae02ebd153
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Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
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2013-08-15 16:35:27 -07:00 |
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Henry Cook
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
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Henry Cook
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
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Henry Cook
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858169917e
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removed dummy DNCs handled by pruning
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2013-08-12 22:34:46 -07:00 |
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Henry Cook
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d9b3c7cfc8
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Moved RenEn to ChiselUtil
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2013-08-12 22:18:25 -07:00 |
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Huy Vo
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387cf0ebe0
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reset -> resetVal, getReset -> reset
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2013-08-12 20:51:54 -07:00 |
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Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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Henry Cook
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de313d97de
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2013-08-02 16:30:09 -07:00 |
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Henry Cook
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
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Henry Cook
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bef6c1db35
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minor nbdcache cleanup
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2013-08-02 16:29:37 -07:00 |
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Stephen Twigg
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3132db4f90
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Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
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2013-07-30 16:36:28 -07:00 |
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Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Henry Cook
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5c00d0a030
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new tilelink arbiter type
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2013-07-09 15:31:46 -07:00 |
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Andrew Waterman
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7cc53c7725
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clean up Str
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2013-06-15 00:45:53 -07:00 |
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Andrew Waterman
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95c5147dc5
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Add RISC-V instruction disassembler
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2013-06-13 10:31:04 -07:00 |
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Henry Cook
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569d8fd796
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Merge branch 'tilelink-data'
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2013-05-23 14:14:40 -07:00 |
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Henry Cook
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12205b9684
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remove obsolete config file reader prototype
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2013-05-23 14:09:03 -07:00 |
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Andrew Waterman
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fe9adfe71b
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Simplify and correct integer multiplier
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2013-05-22 17:27:50 -07:00 |
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Yunsup Lee
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11133d6d4c
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clock gate s2 registers in the frontend
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2013-05-21 18:59:21 -07:00 |
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Yunsup Lee
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c837c1d800
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fix bug in previous JALR commit
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
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2013-05-21 18:28:44 -07:00 |
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Henry Cook
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69b508ff39
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ported caches and htif to use new tilelink
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2013-05-21 17:21:04 -07:00 |
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Andrew Waterman
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28f914c3f2
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don't JALR to speculatively-bypassed addresses
Technically not necessary, but probably improves performance.
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2013-05-21 16:56:58 -07:00 |
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Yunsup Lee
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dcde377303
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Fix DM I$ deadlock
BTB predictions were causing infinite miss loops
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2013-05-20 15:22:58 -07:00 |
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Andrew Waterman
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3a1b5f01b2
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don't take interrupts while they're disabled!
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
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2013-05-19 23:27:47 -07:00 |
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Andrew Waterman
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6eb4c2542a
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comment out I$ assert for now
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2013-05-18 18:09:23 -07:00 |
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Andrew Waterman
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1dab984231
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use UFix instead of Bits for arithmetic
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2013-05-18 00:45:29 -07:00 |
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Andrew Waterman
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dfa7a03f73
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use assert, not Assert
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2013-05-18 00:45:13 -07:00 |
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Andrew Waterman
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d405ffa949
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assume all I$ grants bear data
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2013-05-01 21:01:20 -07:00 |
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Andrew Waterman
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474d321cc7
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fix meta hazard counter to reset on new meta writes
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2013-05-01 16:35:24 -07:00 |
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Andrew Waterman
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a6a88fce19
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Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
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2013-05-01 16:34:45 -07:00 |
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Andrew Waterman
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63a38e7982
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Revert "temp"
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
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2013-05-01 16:34:33 -07:00 |
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Henry Cook
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b6945408cb
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temp
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2013-05-01 10:24:36 -07:00 |
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