181b11bf20
allow Comparator to disable prefetches (for testing BroadcastHub)
2016-06-16 15:14:02 -07:00
a43a93b55c
add BRAMSlave unittest
2016-06-16 15:13:40 -07:00
25ade44fe3
Don't build the Verilator man pages ( #141 )
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These failed for Andrew earlier. While it might be paranioa, there's
really no reason to build the man pages so we might as well not bother.
2016-06-16 10:13:21 -07:00
ba35712f08
Merge pull request #140 from ucb-bar/verilator
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Default to Chisel 3
2016-06-15 16:25:07 -07:00
0b4c8e9af7
Add D-mode single-step support
2016-06-15 16:21:24 -07:00
2d2096e509
Add smaller ROM/RAM for 32-bit debug ( #60 )
2016-06-15 15:07:43 -07:00
68ba33369b
Default to Chisel 3
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Now that we can test Chisel 3 on Travis, I think it's time to turn it on
for everyone else.
2016-06-15 14:01:43 -07:00
e617bb8aa8
Start testing Chisel 3 in Travis
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Now that we have verilator support we can start testing the Chisel 3
Verilog on Travis. This disables Chisel 2 Travis tests because they're
too slow.
2016-06-15 14:01:22 -07:00
f6432395cb
Allow the regressions to run more than once
2016-06-14 21:21:44 -07:00
1525b4717e
Install Verilator when building the emulator
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We need a fairly new version of Verilator, so I just added a rule to
download and install it on all systems.
2016-06-14 21:21:43 -07:00
1c2c9f8ed1
bump rocket to fix RoccExampleConfig
2016-06-14 21:21:06 -07:00
377de06b72
fix comparator Chisel2 compilation issue
2016-06-14 18:36:38 -07:00
b7c0d0cb4d
test both cached and uncached cases in MixedAllocPutRegression
2016-06-14 17:32:29 -07:00
e3816d5fc7
set invalidate_lr in other rocc examples ( #47 )
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This should fix https://travis-ci.org/ucb-bar/rocket-chip/jobs/137607305
2016-06-14 16:59:37 -07:00
571b5b2093
Prevent sbt from running multiple times in emulator
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If you have multi-target rules that don't have %s in them, make
interprets that as "run this recipe multiple times, once to produce each
target". If you have %s in the rules, then make interprets it as "run
this recipe once to produce all targets". We want the second one.
2016-06-14 11:59:20 -07:00
3ce8dbb6e5
fix make error mixing implicit and normal rules
2016-06-14 11:59:20 -07:00
1074c9fe6d
change the way regression IOs are assigned
2016-06-14 11:06:45 -07:00
e284257052
fully disable the cache when not using it in regression tests
2016-06-14 11:06:45 -07:00
3e105eb352
make sure MixedAllocPutRegression uses a block that hasn't been cached already
2016-06-13 18:17:48 -07:00
fe8d81958f
fix groundtests to fit new way of parameterizing TileLink clients
2016-06-13 16:17:27 -07:00
a921458758
add a regression test for no-alloc Put following an alloc Put
2016-06-13 16:17:27 -07:00
e3b4b55836
Refactor breakpoints and support range comparison (currently disabled)
2016-06-10 19:55:58 -07:00
82cef6fa7b
Make a TileLink to Smi converter availiable to users ( #136 )
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See the cooresponding uncore commit for details.
2016-06-10 18:49:17 -07:00
0c695d8e83
Use the new TileLink to Smi converter ( #10 )
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I pulled out the TileLink to Smi converter and put it in uncore so I can
use it for my own stuff.
2016-06-10 14:04:48 -07:00
e5cfc2dac1
Add a Smi to TileLink converter ( #59 )
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I'm trying to get someone to attach their stuff to Rocket Chip for the
upcoming tapout. TileLink sounded too complicated, but Smi went over
well. Since the mmioNetwork in Rocket Chip is based on TileLink, it
seemed like the easiest thing to do was to write a TileLink to Smi
converter so people could use it.
It turns out there was already one inside the groundtest unit tests, so
I just moved that into uncore (it was inlined into a test case so you
couldn't actually use it before). Internally the converter uses Nasti,
but I figured that's good enough for now.
2016-06-10 14:04:28 -07:00
b79db89c03
Update breakpoint spec
2016-06-09 19:13:55 -07:00
c8c7246cce
Update breakpoint spec
2016-06-09 19:07:21 -07:00
2c325151bf
pass invalidate_lr through simple cache interface ( #45 )
2016-06-09 17:22:36 -07:00
70d92995df
TestConfigs: add comparator config
2016-06-09 15:43:13 -07:00
3e51a8bb7a
submodules: include new ComparatorTile
2016-06-09 15:43:13 -07:00
1679cf4764
fix groundtest tilelink xacts
2016-06-09 15:42:44 -07:00
cee0cf345e
[debug] Update Debug ROM contents to write F..F to RAM in case of exception
2016-06-09 14:05:30 -07:00
5562241a50
comparator: a new TileLink stress-tester
2016-06-09 14:02:35 -07:00
586c1079d0
Fix D$ for set size > page size
2016-06-09 13:02:28 -07:00
dca55a2b35
Respect breakpoint privilege settings
2016-06-09 12:41:52 -07:00
c85ea7b987
Set badaddr on breakpoints
2016-06-09 12:33:43 -07:00
4cd77cef10
Make dcsr.halt writable
2016-06-09 12:30:09 -07:00
8516e38eb2
remove implicit modulo addressing in FPU ( #44 )
2016-06-09 11:33:33 -07:00
a1ebc73477
tilelink: don't accidentally make a malformed union
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Closes #55
2016-06-09 10:44:00 -07:00
31b72625aa
ahb: allow no-ops to progress also when a slave is !hready
2016-06-09 10:41:12 -07:00
7014eef339
ahb: fix bugs found using comparatortest
2016-06-09 10:41:11 -07:00
40b6e44816
name resetSignal parameter to tile constructor
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if the tile constructor were to change groundtest
only needs to be updated if resetSignal is removed or renamed
2016-06-09 10:20:48 -07:00
9e86b9efc9
Add provisional breakpoint support
2016-06-08 22:34:19 -07:00
73ed4ea07b
grammar
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English major I'm not, but my sister was and she says 'who' is correct here
2016-06-08 22:34:14 -07:00
93c1b17b52
[debug] Remove erroneous buffer on SB read data ( #56 )
2016-06-08 23:31:13 -04:00
e3c17b5f74
Add provisional breakpoint support
2016-06-08 20:19:52 -07:00
21feeb4a4f
have multiple outstanding requests in CacheFillTest
2016-06-08 19:53:42 -07:00
ed9fcea7f8
hasti: correct fix to locking
2016-06-08 16:28:30 -07:00
ad4e4f19be
Revert "Don't rely on Mux1H output when no inputs are hot"
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This reverts commit b912b7cd1263d7f3b63e6fcb052d9d7493d1b970.
2016-06-08 16:28:30 -07:00
3393d4362b
hasti: fix test SRAM depth
2016-06-08 16:28:30 -07:00
