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Commit Graph

3339 Commits

Author SHA1 Message Date
Andrew Waterman
fc46daecf6 don't flush pipeline on writes to side-effect-free PCRs
notably, K0, K1, and EPC
2013-04-04 17:07:09 -07:00
Andrew Waterman
8b439ef20d only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
2013-04-04 17:07:08 -07:00
Andrew Waterman
d43f484feb take interrupts on nonzero fromhost values 2013-04-04 17:07:08 -07:00
Andrew Waterman
d4a3351cfc expose pending interrupts in status register 2013-04-04 17:07:08 -07:00
Henry Cook
c6b56c5f25 bump rocket for coherence bug fix 2013-04-04 15:52:20 -07:00
Henry Cook
f8aebcbf8c fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match 2013-04-04 15:50:29 -07:00
Henry Cook
9d5e97d89e override io in LogicalNetwork 2013-03-28 14:10:20 -07:00
Henry Cook
b6cc08e8ca override io in LogicalNetwork 2013-03-28 14:09:48 -07:00
Henry Cook
16ad8a7e9c Fixes after merge 2013-03-25 19:14:38 -07:00
Henry Cook
67fc09f62e Fixes after merge, and always self probe. 2013-03-25 19:12:19 -07:00
Henry Cook
16113a96ba fixes after merge 2013-03-25 19:09:08 -07:00
Andrew Waterman
8e926f8d79 remove aborts 2013-03-25 17:01:46 -07:00
Henry Cook
eec590c1bf Added support for multiple L2 banks. Moved tile IO queueing. 2013-03-25 17:01:46 -07:00
Henry Cook
806f897fc4 nTiles -> nClients in LogicalNetworkConfig 2013-03-25 17:01:46 -07:00
Andrew Waterman
ce4c1aa566 remove aborts 2013-03-25 17:01:46 -07:00
Henry Cook
cf76665d09 writebacks on release network pass asm tests and bmarks 2013-03-25 17:01:46 -07:00
Henry Cook
a0dc8d52d6 using new network and l2 controller 2013-03-25 17:01:46 -07:00
Andrew Waterman
def11e44b8 don't pipe stdout to vcd2vpd 2013-03-25 17:01:13 -07:00
Andrew Waterman
ef4927c9ad use a named pipe for VCD -> VPD conversion 2013-03-25 16:19:19 -07:00
Henry Cook
06f5de3b68 Merge branch 'release-xacts'
Conflicts:
	src/package.scala
	src/uncore.scala
2013-03-20 17:38:46 -07:00
Henry Cook
95f0a688e9 Merge branch 'release-xacts'
Conflicts:
	src/htif.scala
	src/icache.scala
	src/nbdcache.scala
	src/tile.scala
2013-03-20 17:37:50 -07:00
Henry Cook
4d007d5c40 changed val names in hub to match new tilelink names 2013-03-20 17:14:07 -07:00
Henry Cook
273bd34091 Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants. 2013-03-20 15:53:36 -07:00
Henry Cook
c36b1dfa30 Cleaned up uncore and coherence interface. Removed defunct broadcast hub. Trait-ified tilelink bundle components. Added generalized mem arbiter. 2013-03-20 15:52:39 -07:00
Henry Cook
319b4544d7 nTiles -> nClients in LogicalNetworkConfig 2013-03-20 14:30:16 -07:00
Henry Cook
a7ae7e5758 Cleaned up self-probes 2013-03-20 14:28:20 -07:00
Henry Cook
6d2541aced nTiles -> nClients in LogicalNetworkConfig 2013-03-20 14:12:36 -07:00
Andrew Waterman
7b019cb0da rmeove aborts 2013-03-19 15:30:23 -07:00
Andrew Waterman
ea9d0b771e remove aborts; simplify probes 2013-03-19 15:29:40 -07:00
Yunsup Lee
bc140ce9bc add vec_{vvadd,cmplxmult,matmul} bmarks 2013-03-19 00:43:51 -07:00
Yunsup Lee
9efe71412f add DRAMSideLLCNull 2013-03-19 00:43:34 -07:00
Yunsup Lee
0f50970913 move HellaQueue to uncore 2013-03-19 00:43:20 -07:00
Yunsup Lee
f120800aa2 add DRAMSideLLCNull 2013-03-19 00:41:28 -07:00
Yunsup Lee
717a78f964 fix seqRead inference 2013-03-19 00:41:09 -07:00
Henry Cook
9f0ccbeac5 writebacks on release network pass asm tests and bmarks 2013-02-28 18:13:41 -08:00
Henry Cook
e0361840bd writebacks on release network pass asm tests and bmarks 2013-02-28 18:11:40 -08:00
Andrew Waterman
944f56a766 remove duplicate definitions 2013-02-28 14:55:19 -08:00
Andrew Waterman
c6695bee7c fix emulator HTIF interface bug 2013-02-20 16:11:21 -08:00
Andrew Waterman
fc26150933 update to new Mem style 2013-02-20 16:10:47 -08:00
Andrew Waterman
35349d227f update to new Mem style 2013-02-20 16:09:46 -08:00
Eric Love
17b8654042 Merge branch 'master' of github.com:ucb-bar/reference-chip 2013-02-12 12:47:03 -06:00
Yunsup Lee
61b18a6722 push rocket,hwacha,uncore 2013-02-09 01:05:51 -08:00
Andrew Waterman
9f89c812b7 fix HTIF memory size reporting 2013-01-29 23:08:25 -08:00
Yunsup Lee
a0bd0adeb2 change write/read port ordering for vlsi_mem_gen script 2013-01-29 21:32:42 -08:00
Andrew Waterman
66eb3720a4 fix SRAM semantics bug in HellaFlowQueue 2013-01-29 21:16:42 -08:00
Yunsup Lee
60bd3a6413 Revert "shuffled FPU control logic around to make functional unit retiming work better"
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
2013-01-29 19:34:55 -08:00
Andrew Waterman
6275e009f8 fix HellaQueue deq.valid signal 2013-01-28 20:57:43 -08:00
Andrew Waterman
45d8066f45 add HellaQueue, an SRAM-based queue 2013-01-28 20:54:25 -08:00
Andrew Waterman
37c67f1d87 pipeline reset to the vector unit 2013-01-28 17:56:32 -08:00
Rimas Avizienis
f2df6147df shuffled FPU control logic around to make functional unit retiming work better 2013-01-28 17:17:09 -08:00