nTiles -> nClients in LogicalNetworkConfig
This commit is contained in:
Henry Cook
parent
ce4c1aa566
commit
806f897fc4
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@ -22,7 +22,7 @@ class TileToCrossbarShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetwork
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val in = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}.flip
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val out = (new FIFOIO){(new BasicCrossbarIO){ data }}
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}
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io.out.bits.header.src := io.in.bits.header.src + UFix(lconf.nHubs)
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io.out.bits.header.src := io.in.bits.header.src + UFix(lconf.nMasters)
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io.out.bits.header.dst := io.in.bits.header.dst
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io.out.bits.payload := io.in.bits.payload
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io.out.valid := io.in.valid
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@ -42,7 +42,7 @@ class HubToCrossbarShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkC
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val out = (new FIFOIO){(new BasicCrossbarIO){ data }}
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}
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io.out.bits.header.src := io.in.bits.header.src
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io.out.bits.header.dst := io.in.bits.header.dst + UFix(lconf.nHubs)
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io.out.bits.header.dst := io.in.bits.header.dst + UFix(lconf.nMasters)
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io.out.bits.payload := io.in.bits.payload
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io.out.valid := io.in.valid
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io.in.ready := io.out.ready
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@ -61,7 +61,7 @@ class CrossbarToTileShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetwork
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val out = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}
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}
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io.out.bits.header.src := io.in.bits.header.src
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io.out.bits.header.dst := io.in.bits.header.dst - UFix(lconf.nHubs)
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io.out.bits.header.dst := io.in.bits.header.dst - UFix(lconf.nMasters)
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io.out.bits.payload := io.in.bits.payload
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io.out.valid := io.in.valid
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io.in.ready := io.out.ready
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@ -79,7 +79,7 @@ class CrossbarToHubShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkC
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val in = (new FIFOIO){(new BasicCrossbarIO){ data }}.flip
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val out = (new MasterSourcedIO){(new LogicalNetworkIO){ data }}.flip
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}
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io.out.bits.header.src := io.in.bits.header.src - UFix(lconf.nHubs)
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io.out.bits.header.src := io.in.bits.header.src - UFix(lconf.nMasters)
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io.out.bits.header.dst := io.in.bits.header.dst
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io.out.bits.payload := io.in.bits.payload
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io.out.valid := io.in.valid
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@ -201,9 +201,9 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
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{
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implicit val lnconf = conf.ln
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val io = new Bundle {
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val tiles = Vec(conf.ln.nTiles) { new TileLinkIO }.flip
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val tiles = Vec(conf.ln.nClients) { new TileLinkIO }.flip
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val htif = (new TileLinkIO).flip
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val incoherent = Vec(conf.ln.nTiles) { Bool() }.asInput
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val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
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val mem_backup = new ioMemSerialized(htif_width)
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val mem_backup_en = Bool(INPUT)
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val mem = new ioMemPipe
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@ -213,9 +213,9 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
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val lnWithHtifConf = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1,
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idBits = log2Up(conf.ln.nEndpoints+1)+1,
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nTiles = conf.ln.nTiles+1)
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nClients = conf.ln.nClients+1)
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val chWithHtifConf = conf.copy(ln = lnWithHtifConf)
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require(tileEndpoints.length == lnWithHtifConf.nTiles)
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require(tileEndpoints.length == lnWithHtifConf.nClients)
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//val hub = new CoherenceHubBroadcast()(chWithHtifConf)
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val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
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val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
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@ -231,14 +231,14 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
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//hub.io.tiles <> adapter.io.hub
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hub.io.network <> net.io(0)
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for (i <- 1 to conf.ln.nTiles) {
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for (i <- 1 to conf.ln.nClients) {
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net.io(i) <> io.tiles(i-1)
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//hub.io.tiles(i-1) <> io.tiles(i-1)
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hub.io.incoherent(i-1) := io.incoherent(i-1)
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}
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net.io(conf.ln.nTiles+1) <> io.htif
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//hub.io.tiles(conf.ln.nTiles) <> io.htif
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hub.io.incoherent(conf.ln.nTiles) := Bool(true)
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net.io(conf.ln.nClients+1) <> io.htif
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//hub.io.tiles(conf.ln.nClients) <> io.htif
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hub.io.incoherent(conf.ln.nClients) := Bool(true)
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llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd)
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llc.io.cpu.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES)
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@ -276,9 +276,9 @@ class Uncore(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit
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val mem_backup = new ioMemSerialized(htif_width)
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val mem_backup_en = Bool(INPUT)
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val mem = new ioMemPipe
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val tiles = Vec(conf.ln.nTiles) { new TileLinkIO }.flip
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val htif = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles) }.flip
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val incoherent = Vec(conf.ln.nTiles) { Bool() }.asInput
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val tiles = Vec(conf.ln.nClients) { new TileLinkIO }.flip
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val htif = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients) }.flip
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val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
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}
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val htif = new rocketHTIF(htif_width)
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@ -11,20 +11,20 @@ class FPGAUncore(htif_width: Int)(implicit conf: CoherenceHubConfiguration) exte
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val io = new Bundle {
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val host = new HostIO(htif_width)
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val mem = new ioMem
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val tiles = Vec(conf.ln.nTiles) { new TileLinkIO()(conf.ln) }.flip
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val htif = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles) }.flip
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val incoherent = Vec(conf.ln.nTiles) { Bool() }.asInput
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val tiles = Vec(conf.ln.nClients) { new TileLinkIO()(conf.ln) }.flip
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val htif = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients) }.flip
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val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
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}
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val htif = new rocketHTIF(htif_width)
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htif.io.cpu <> io.htif
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io.host <> htif.io.host
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val lnWithHtif = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1, nTiles = conf.ln.nTiles+1)
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val lnWithHtif = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1, nClients = conf.ln.nClients+1)
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val hub = new CoherenceHubBroadcast()(conf.copy(ln = lnWithHtif))
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for (i <- 0 until conf.ln.nTiles)
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for (i <- 0 until conf.ln.nClients)
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hub.io.tiles(i) <> io.tiles(i)
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hub.io.tiles(conf.ln.nTiles) <> htif.io.mem
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hub.io.tiles(conf.ln.nClients) <> htif.io.mem
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hub.io.incoherent <> io.incoherent
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io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
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@ -44,17 +44,17 @@ class FPGATop extends Component {
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implicit val uconf = CoherenceHubConfiguration(co, lnConf)
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val uncore = new FPGAUncore(htif_width = htif_width)
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val resetSigs = Vec(uconf.ln.nTiles){ Bool() }
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val resetSigs = Vec(uconf.ln.nClients){ Bool() }
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val ic = ICacheConfig(64, 1, co, ntlb = 4, nbtb = 4)
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val dc = DCacheConfig(64, 1, co, ntlb = 4,
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nmshr = 2, nrpq = 16, nsdq = 17)
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val rc = RocketConfiguration(uconf.ln, co, ic, dc,
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fastMulDiv = false,
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fpu = false, vec = false)
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val tileList = (0 until uconf.ln.nTiles).map(r => new Tile(resetSignal = resetSigs(r))(rc))
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val tileList = (0 until uconf.ln.nClients).map(r => new Tile(resetSignal = resetSigs(r))(rc))
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io.debug.error_mode := Bool(false)
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for (i <- 0 until uconf.ln.nTiles) {
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for (i <- 0 until uconf.ln.nClients) {
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val hl = uncore.io.htif(i)
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val tl = uncore.io.tiles(i)
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val il = uncore.io.incoherent(i)
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