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riscv
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rocket-chip
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a0bd0adeb2f075e6af8d3b7efeaaae62a143887a
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Yunsup Lee
a0bd0adeb2
change write/read port ordering for vlsi_mem_gen script
2013-01-29 21:32:42 -08:00
rocket/src/main
/scala
change write/read port ordering for vlsi_mem_gen script
2013-01-29 21:32:42 -08:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%