nTiles -> nClients in LogicalNetworkConfig
This commit is contained in:
Henry Cook
parent
a7ae7e5758
commit
319b4544d7
@ -48,7 +48,7 @@ class BasicCrossbar[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfi
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}
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}
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case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int, nHubs: Int, nTiles: Int)
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case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int, nMasters: Int, nClients: Int)
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abstract class LogicalNetwork[TileLinkType <: Bundle](endpoints: Seq[CoherenceAgentRole])(implicit conf: LogicalNetworkConfiguration) extends Component {
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val io: Vec[TileLinkType]
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@ -24,9 +24,9 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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val p_data = (new PipeIO) { new TrackerProbeData }.flip
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val can_alloc = Bool(INPUT)
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val grant_ack = Bool(INPUT)
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val release_cnt_dec = Bits(INPUT, conf.ln.nTiles)
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val probe_cnt_inc = Bits(INPUT, conf.ln.nTiles)
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val tile_incoherent = Bits(INPUT, conf.ln.nTiles)
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val release_cnt_dec = Bits(INPUT, conf.ln.nClients)
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val probe_cnt_inc = Bits(INPUT, conf.ln.nClients)
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val tile_incoherent = Bits(INPUT, conf.ln.nClients)
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val release_data = (new PipeIO) { new ReleaseData }.flip
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val acquire_data = (new PipeIO) { new AcquireData }.flip
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val sent_grant_ack = Bool(INPUT)
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@ -44,13 +44,13 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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val client_xact_id = Bits(OUTPUT, CLIENT_XACT_ID_BITS)
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val sharer_count = Bits(OUTPUT, conf.ln.idBits+1)
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val a_type = Bits(OUTPUT, ACQUIRE_TYPE_MAX_BITS)
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val push_probe = Bits(OUTPUT, conf.ln.nTiles)
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val pop_release = Bits(OUTPUT, conf.ln.nTiles)
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val pop_release_data = Bits(OUTPUT, conf.ln.nTiles)
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val pop_release_dep = Bits(OUTPUT, conf.ln.nTiles)
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val pop_acquire = Bits(OUTPUT, conf.ln.nTiles)
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val pop_acquire_data = Bits(OUTPUT, conf.ln.nTiles)
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val pop_acquire_dep = Bits(OUTPUT, conf.ln.nTiles)
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val push_probe = Bits(OUTPUT, conf.ln.nClients)
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val pop_release = Bits(OUTPUT, conf.ln.nClients)
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val pop_release_data = Bits(OUTPUT, conf.ln.nClients)
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val pop_release_dep = Bits(OUTPUT, conf.ln.nClients)
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val pop_acquire = Bits(OUTPUT, conf.ln.nClients)
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val pop_acquire_data = Bits(OUTPUT, conf.ln.nClients)
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val pop_acquire_dep = Bits(OUTPUT, conf.ln.nClients)
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val send_grant_ack = Bool(OUTPUT)
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}
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@ -91,8 +91,8 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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val state = Reg(resetVal = s_idle)
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val xact = Reg{ new Acquire }
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val init_client_id_ = Reg{ Bits() }
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val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles))
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val release_count = if (conf.ln.nClients == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients)))
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val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nClients))
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val release_client_id_ = Reg{ Bits() }
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val x_needs_read = Reg(resetVal = Bool(false))
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val acquire_data_needs_write = Reg(resetVal = Bool(false))
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@ -102,11 +102,11 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES))
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val probe_initial_flags = Bits(width = conf.ln.nTiles)
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val probe_initial_flags = Bits(width = conf.ln.nClients)
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probe_initial_flags := Bits(0)
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if (conf.ln.nTiles > 1) {
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if (conf.ln.nClients > 1) {
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val probe_self = co.needsSelfProbe(io.alloc_req.bits.acquire)
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val probe_self_flag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nTiles)-1,0)))
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val probe_self_flag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nClients)-1,0)))
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probe_initial_flags := ~(io.tile_incoherent | probe_self_flag)
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}
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@ -115,7 +115,7 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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io.init_client_id := init_client_id_
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io.release_client_id := release_client_id_
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io.client_xact_id := xact.client_xact_id
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io.sharer_count := UFix(conf.ln.nTiles) // TODO: Broadcast only
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io.sharer_count := UFix(conf.ln.nClients) // TODO: Broadcast only
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io.a_type := xact.a_type
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io.mem_req_cmd.valid := Bool(false)
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@ -129,13 +129,13 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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io.probe.bits.p_type := co.getProbeType(xact.a_type, UFix(0))
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io.probe.bits.master_xact_id := UFix(id)
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io.probe.bits.addr := xact.addr
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io.push_probe := Bits(0, width = conf.ln.nTiles)
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io.pop_release := Bits(0, width = conf.ln.nTiles)
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io.pop_release_data := Bits(0, width = conf.ln.nTiles)
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io.pop_release_dep := Bits(0, width = conf.ln.nTiles)
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io.pop_acquire := Bits(0, width = conf.ln.nTiles)
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io.pop_acquire_data := Bits(0, width = conf.ln.nTiles)
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io.pop_acquire_dep := Bits(0, width = conf.ln.nTiles)
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io.push_probe := Bits(0, width = conf.ln.nClients)
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io.pop_release := Bits(0, width = conf.ln.nClients)
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io.pop_release_data := Bits(0, width = conf.ln.nClients)
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io.pop_release_dep := Bits(0, width = conf.ln.nClients)
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io.pop_acquire := Bits(0, width = conf.ln.nClients)
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io.pop_acquire_data := Bits(0, width = conf.ln.nClients)
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io.pop_acquire_dep := Bits(0, width = conf.ln.nClients)
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io.send_grant_ack := Bool(false)
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switch (state) {
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@ -150,7 +150,7 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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p_w_mem_cmd_sent := Bool(false)
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x_w_mem_cmd_sent := Bool(false)
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io.pop_acquire := UFix(1) << io.alloc_req.bits.client_id
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if(conf.ln.nTiles > 1) {
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if(conf.ln.nClients > 1) {
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release_count := PopCount(probe_initial_flags)
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state := Mux(probe_initial_flags.orR, s_probe, s_mem)
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} else state := s_mem
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@ -167,7 +167,7 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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when(io.release_cnt_dec.orR) {
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val dec = PopCount(io.release_cnt_dec)
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io.pop_release := io.release_cnt_dec
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if(conf.ln.nTiles > 1) release_count := release_count - dec
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if(conf.ln.nClients > 1) release_count := release_count - dec
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when(release_count === dec) {
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state := s_mem
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}
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@ -223,7 +223,7 @@ case class CoherenceHubConfiguration(co: CoherencePolicy, ln: LogicalNetworkConf
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class CoherenceHubAdapter(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent {
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val io = new Bundle {
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val net = (new TileLinkIO).flip
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val hub = Vec(conf.nTiles) { new TileLinkIO }
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val hub = Vec(conf.nClients) { new TileLinkIO }
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}
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val netClientProducedSubBundles = io.net.getClass.getMethods.filter( x =>
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@ -259,8 +259,8 @@ class CoherenceHubAdapter(implicit conf: LogicalNetworkConfiguration) extends Co
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abstract class CoherenceHub(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent {
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val io = new Bundle {
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val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
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val incoherent = Vec(conf.nTiles) { Bool() }.asInput
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val tiles = Vec(conf.nClients) { new TileLinkIO }.flip
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val incoherent = Vec(conf.nClients) { Bool() }.asInput
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val mem = new ioMem
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}
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}
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@ -307,8 +307,8 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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val send_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() }
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val do_free_arr = Vec(NGLOBAL_XACTS){ Bool() }
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val release_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} }
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val probe_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} }
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val release_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nClients){ Bool()} }
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val probe_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nClients){ Bool()} }
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val sent_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() }
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val p_data_client_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) }
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val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Bool() }
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@ -333,17 +333,17 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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sent_grant_ack_arr(i) := Bool(false)
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p_data_client_id_arr(i) := Bits(0, width = conf.ln.idBits)
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p_data_valid_arr(i) := Bool(false)
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for( j <- 0 until conf.ln.nTiles) {
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for( j <- 0 until conf.ln.nClients) {
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release_cnt_dec_arr(i)(j) := Bool(false)
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probe_cnt_inc_arr(i)(j) := Bool(false)
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}
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}
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val release_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
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val acquire_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
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val release_data_dep_list = List.fill(conf.ln.nClients)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
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val acquire_data_dep_list = List.fill(conf.ln.nClients)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
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// Free finished transactions
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for( j <- 0 until conf.ln.nTiles ) {
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for( j <- 0 until conf.ln.nClients ) {
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val ack = io.tiles(j).grant_ack
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when (ack.valid) {
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do_free_arr(ack.bits.payload.master_xact_id) := Bool(true)
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@ -355,7 +355,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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// Forward memory responses from mem to tile or arbitrate to ack
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val mem_idx = io.mem.resp.bits.tag
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val ack_idx = PriorityEncoder(send_grant_ack_arr.toBits)
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for( j <- 0 until conf.ln.nTiles ) {
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for( j <- 0 until conf.ln.nClients ) {
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val rep = io.tiles(j).grant
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rep.bits.payload.g_type := UFix(0)
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rep.bits.payload.client_xact_id := UFix(0)
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@ -393,7 +393,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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io.mem.req_data <> Queue(mem_req_data_arb.io.out)
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// Handle probe replies, which may or may not have data
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for( j <- 0 until conf.ln.nTiles ) {
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for( j <- 0 until conf.ln.nClients ) {
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val release = io.tiles(j).release
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val release_data = io.tiles(j).release_data
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val idx = release.bits.payload.master_xact_id
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@ -413,10 +413,10 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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trackerList(i).io.release_data.valid := io.tiles(trackerList(i).io.release_client_id).release_data.valid
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trackerList(i).io.release_data.bits := io.tiles(trackerList(i).io.release_client_id).release_data.bits.payload
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trackerList(i).io.release_data_dep.valid := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> release_data_dep_list(j).io.deq.valid))
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trackerList(i).io.release_data_dep.bits := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> release_data_dep_list(j).io.deq.bits))
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trackerList(i).io.release_data_dep.valid := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.valid, (0 until conf.ln.nClients).map( j => UFix(j) -> release_data_dep_list(j).io.deq.valid))
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trackerList(i).io.release_data_dep.bits := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.bits, (0 until conf.ln.nClients).map( j => UFix(j) -> release_data_dep_list(j).io.deq.bits))
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for( j <- 0 until conf.ln.nTiles) {
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for( j <- 0 until conf.ln.nClients) {
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val release = io.tiles(j).release
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release_cnt_dec_arr(i)(j) := release.valid && (release.bits.payload.master_xact_id === UFix(i))
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}
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@ -426,7 +426,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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// Only one allocation per cycle
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// Init requests may or may not have data
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val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() }
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val init_arb = (new Arbiter(conf.ln.nTiles)) { new TrackerAllocReq }
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val init_arb = (new Arbiter(conf.ln.nClients)) { new TrackerAllocReq }
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for( i <- 0 until NGLOBAL_XACTS ) {
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alloc_arb.io.in(i).valid := !trackerList(i).io.busy
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trackerList(i).io.can_alloc := alloc_arb.io.in(i).ready
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@ -435,10 +435,10 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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trackerList(i).io.acquire_data.bits := io.tiles(trackerList(i).io.init_client_id).acquire_data.bits.payload
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trackerList(i).io.acquire_data.valid := io.tiles(trackerList(i).io.init_client_id).acquire_data.valid
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trackerList(i).io.acquire_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.bits))
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trackerList(i).io.acquire_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.valid))
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trackerList(i).io.acquire_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.bits, (0 until conf.ln.nClients).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.bits))
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trackerList(i).io.acquire_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.valid, (0 until conf.ln.nClients).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.valid))
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}
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for( j <- 0 until conf.ln.nTiles ) {
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for( j <- 0 until conf.ln.nClients ) {
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val acquire = io.tiles(j).acquire
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val acquire_data = io.tiles(j).acquire_data
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val acquire_data_dep = acquire_data_dep_list(j).io.deq
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@ -457,8 +457,8 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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// Handle probe request generation
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// Must arbitrate for each request port
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val probe_arb_arr = List.fill(conf.ln.nTiles)((new Arbiter(NGLOBAL_XACTS)) { new Probe() })
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for( j <- 0 until conf.ln.nTiles ) {
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val probe_arb_arr = List.fill(conf.ln.nClients)((new Arbiter(NGLOBAL_XACTS)) { new Probe() })
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for( j <- 0 until conf.ln.nClients ) {
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for( i <- 0 until NGLOBAL_XACTS ) {
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val t = trackerList(i).io
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probe_arb_arr(j).io.in(i).bits := t.probe.bits
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@ -473,7 +473,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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abstract class CoherenceAgent(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent {
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val io = new Bundle {
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val network = (new TileLinkIO).flip
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val incoherent = Vec(conf.nTiles) { Bool() }.asInput
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val incoherent = Vec(conf.nClients) { Bool() }.asInput
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val mem = new ioMem
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}
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}
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@ -604,7 +604,7 @@ abstract class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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val release = (new FIFOIO){(new LogicalNetworkIO) { new Release }}.flip
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val release_data = (new FIFOIO){(new LogicalNetworkIO) { new ReleaseData }}.flip
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val free = Bool(INPUT)
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val tile_incoherent = Bits(INPUT, conf.ln.nTiles)
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val tile_incoherent = Bits(INPUT, conf.ln.nClients)
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val release_data_dep = (new FIFOIO) { new TrackerDependency }.flip
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val acquire_data_dep = (new FIFOIO) { new TrackerDependency }.flip
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val mem_resp = (new FIFOIO) { new MemResp }.flip
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@ -624,7 +624,7 @@ class WritebackTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extend
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val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(4){ UFix() }
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val state = Reg(resetVal = s_idle)
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val xact = Reg{ new Release }
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val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients)))
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val release_data_needs_write = Reg(resetVal = Bool(false))
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val mem_cmd_sent = Reg(resetVal = Bool(false))
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@ -688,27 +688,27 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends
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val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() }
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val state = Reg(resetVal = s_idle)
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val xact = Reg{ new Acquire }
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val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients)))
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//TODO: Will need id reg for merged release xacts
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val init_sharer_cnt_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val init_sharer_cnt_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients)))
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val grant_type = co.getGrantType(xact.a_type, init_sharer_cnt_)
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val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles))
|
||||
val release_count = if (conf.ln.nClients == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients)))
|
||||
val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nClients))
|
||||
val x_needs_read = Reg(resetVal = Bool(false))
|
||||
val acquire_data_needs_write = Reg(resetVal = Bool(false))
|
||||
val release_data_needs_write = Reg(resetVal = Bool(false))
|
||||
val x_w_mem_cmd_sent = Reg(resetVal = Bool(false))
|
||||
val p_w_mem_cmd_sent = Reg(resetVal = Bool(false))
|
||||
val probe_initial_flags = Bits(width = conf.ln.nTiles)
|
||||
val probe_initial_flags = Bits(width = conf.ln.nClients)
|
||||
probe_initial_flags := Bits(0)
|
||||
if (conf.ln.nTiles > 1) {
|
||||
if (conf.ln.nClients > 1) {
|
||||
// issue self-probes for uncached read xacts to facilitate I$ coherence
|
||||
// TODO: this is hackish; figure out how to do it more systematically
|
||||
val probe_self = co match {
|
||||
case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.acquire.bits.payload)
|
||||
case _ => Bool(false)
|
||||
}
|
||||
val myflag = Mux(probe_self, Bits(0), UFixToOH(io.acquire.bits.header.src(log2Up(conf.ln.nTiles)-1,0)))
|
||||
val myflag = Mux(probe_self, Bits(0), UFixToOH(io.acquire.bits.header.src(log2Up(conf.ln.nClients)-1,0)))
|
||||
probe_initial_flags := ~(io.tile_incoherent | myflag)
|
||||
}
|
||||
|
||||
@ -746,7 +746,7 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends
|
||||
when( io.acquire.valid ) {
|
||||
xact := io.acquire.bits.payload
|
||||
init_client_id_ := io.acquire.bits.header.src
|
||||
init_sharer_cnt_ := UFix(conf.ln.nTiles) // TODO: Broadcast only
|
||||
init_sharer_cnt_ := UFix(conf.ln.nClients) // TODO: Broadcast only
|
||||
acquire_data_needs_write := co.messageHasData(io.acquire.bits.payload)
|
||||
x_needs_read := co.needsMemRead(io.acquire.bits.payload.a_type, UFix(0))
|
||||
probe_flags := probe_initial_flags
|
||||
@ -754,7 +754,7 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends
|
||||
p_w_mem_cmd_sent := Bool(false)
|
||||
x_w_mem_cmd_sent := Bool(false)
|
||||
io.acquire.ready := Bool(true)
|
||||
if(conf.ln.nTiles > 1) {
|
||||
if(conf.ln.nClients > 1) {
|
||||
release_count := PopCount(probe_initial_flags)
|
||||
state := Mux(probe_initial_flags.orR, s_probe, s_mem)
|
||||
} else state := s_mem
|
||||
@ -771,7 +771,7 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends
|
||||
}
|
||||
when(io.release.valid) {
|
||||
io.release.ready := Bool(true)
|
||||
if(conf.ln.nTiles > 1) release_count := release_count - UFix(1)
|
||||
if(conf.ln.nClients > 1) release_count := release_count - UFix(1)
|
||||
when(release_count === UFix(1)) {
|
||||
state := s_mem
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user