add DRAMSideLLCNull
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Submodule riscv-rocket updated: be69e6ce1d...76cb0d00d5
@ -220,6 +220,7 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
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val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
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val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
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val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
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//val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES)
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val mem_serdes = new MemSerdes(htif_width)
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val hub = new CoherenceHubBroadcast()(chWithHtifConf)
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2
uncore
2
uncore
Submodule uncore updated: 716d708544...bf8c0b248a
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