Added support for multiple L2 banks. Moved tile IO queueing.
This commit is contained in:
Henry Cook
parent
806f897fc4
commit
eec590c1bf
@ -2,6 +2,7 @@ package referencechip
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import Chisel._
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import Node._
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import uncore.Constants._
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import uncore._
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import rocket._
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import rocket.Util._
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@ -9,6 +10,122 @@ import ReferenceChipBackend._
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import scala.collection.mutable.ArrayBuffer
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import scala.collection.mutable.HashMap
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object TileLinkHeaderAppender {
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def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](meta: ClientSourcedIO[LogicalNetworkIO[T]], data: ClientSourcedIO[LogicalNetworkIO[U]], clientId: Int, nBanks: Int, bankIdLsb: Int)(implicit conf: UncoreConfiguration) = {
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val shim = (new TileLinkHeaderAppenderWithData(clientId, nBanks, bankIdLsb)){meta.bits.payload.clone}{data.bits.payload.clone}
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shim.io.meta_in <> meta
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shim.io.data_in <> data
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(shim.io.meta_out, shim.io.data_out)
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}
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def apply[T <: SourcedMessage with HasPhysicalAddress](meta: ClientSourcedIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, bankIdLsb: Int)(implicit conf: UncoreConfiguration) = {
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val shim = (new TileLinkHeaderAppender(clientId, nBanks, bankIdLsb)){meta.bits.payload.clone}
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shim.io.meta_in <> meta
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shim.io.meta_out
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}
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}
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abstract class AddressConverter extends Component {
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def convertAddrToBank(addr: Bits, n: Int, lsb: Int): UFix = {
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require(lsb + log2Up(n) < PADDR_BITS - OFFSET_BITS, {println("Invalid bits for bank multiplexing.")})
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addr(lsb + log2Up(n) - 1, lsb)
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}
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}
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class TileLinkHeaderAppenderWithData[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](clientId: Int, nBanks: Int, bankIdLsb: Int)(metadata: => T)(data: => U)(implicit conf: UncoreConfiguration) extends AddressConverter {
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implicit val ln = conf.ln
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val io = new Bundle {
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val meta_in = (new ClientSourcedIO){(new LogicalNetworkIO){ metadata }}.flip
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val data_in = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}.flip
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val meta_out = (new ClientSourcedIO){(new LogicalNetworkIO){ metadata }}
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val data_out = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}
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}
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val meta_q = Queue(io.meta_in)
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val data_q = Queue(io.data_in)
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if(nBanks == 1) {
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io.meta_out.bits.payload := meta_q.bits.payload
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io.meta_out.bits.header.src := UFix(clientId)
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io.meta_out.bits.header.dst := UFix(0)
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io.meta_out.valid := meta_q.valid
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meta_q.ready := io.meta_out.ready
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io.data_out.bits.payload := data_q.bits.payload
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io.data_out.bits.header.src := UFix(clientId)
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io.data_out.bits.header.dst := UFix(0)
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io.data_out.valid := data_q.valid
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data_q.ready := io.data_out.ready
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} else {
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val meta_has_data = conf.co.messageHasData(meta_q.bits.payload)
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val addr_q = (new Queue(2, pipe = true, flow = true)){io.meta_in.bits.payload.addr.clone}
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val data_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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val data_cnt_up = data_cnt + UFix(1)
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io.meta_out.bits.payload := meta_q.bits.payload
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io.meta_out.bits.header.src := UFix(clientId)
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io.meta_out.bits.header.dst := convertAddrToBank(meta_q.bits.payload.addr, nBanks, bankIdLsb)
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io.data_out.bits.payload := meta_q.bits.payload
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io.data_out.bits.header.src := UFix(clientId)
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io.data_out.bits.header.dst := convertAddrToBank(addr_q.io.deq.bits, nBanks, bankIdLsb)
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addr_q.io.enq.bits := meta_q.bits.payload.addr
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io.meta_out.valid := meta_q.valid && addr_q.io.enq.ready
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meta_q.ready := io.meta_out.ready && addr_q.io.enq.ready
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io.data_out.valid := data_q.valid && addr_q.io.deq.valid
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data_q.ready := io.data_out.ready && addr_q.io.deq.valid
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addr_q.io.enq.valid := meta_q.valid && io.meta_out.ready && meta_has_data
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addr_q.io.deq.ready := Bool(false)
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when(data_q.valid && data_q.ready) {
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data_cnt := data_cnt_up
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when(data_cnt_up === UFix(0)) {
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addr_q.io.deq.ready := Bool(true)
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}
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}
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}
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}
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class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress](clientId: Int, nBanks: Int, bankIdLsb: Int)(metadata: => T)(implicit conf: UncoreConfiguration) extends AddressConverter {
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implicit val ln = conf.ln
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val io = new Bundle {
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val meta_in = (new ClientSourcedIO){(new LogicalNetworkIO){ metadata }}.flip
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val meta_out = (new ClientSourcedIO){(new LogicalNetworkIO){ metadata }}
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}
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val meta_q = Queue(io.meta_in)
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io.meta_out.bits.payload := meta_q.bits.payload
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io.meta_out.bits.header.src := UFix(clientId)
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io.meta_out.valid := meta_q.valid
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meta_q.ready := io.meta_out.ready
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if(nBanks == 1) {
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io.meta_out.bits.header.dst := UFix(0)
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} else {
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io.meta_out.bits.header.dst := convertAddrToBank(meta_q.bits.payload.addr, nBanks, bankIdLsb)
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}
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}
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class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: UncoreConfiguration) extends Component {
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implicit val ln = conf.ln
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val io = new Bundle {
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val uncached = new UncachedTileLinkIO().flip
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val mem = new ioMem
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}
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val mem_cmd_q = (new Queue(qDepth)){new MemReqCmd}
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val mem_data_q = (new Queue(qDepth)){new MemData}
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mem_cmd_q.io.enq.valid := io.uncached.acquire.valid
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io.uncached.acquire.ready := mem_cmd_q.io.enq.ready
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mem_cmd_q.io.enq.bits.rw := conf.co.needsOuterWrite(io.uncached.acquire.bits.payload.a_type, UFix(0))
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mem_cmd_q.io.enq.bits.tag := io.uncached.acquire.bits.payload.client_xact_id
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mem_cmd_q.io.enq.bits.addr := io.uncached.acquire.bits.payload.addr
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mem_data_q.io.enq.valid := io.uncached.acquire_data.valid
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io.uncached.acquire_data.ready := mem_data_q.io.enq.ready
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mem_data_q.io.enq.bits.data := io.uncached.acquire_data.bits.payload.data
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io.uncached.grant.valid := io.mem.resp.valid
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io.mem.resp.ready := io.uncached.grant.ready
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io.uncached.grant.bits.payload.data := io.mem.resp.bits.data
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io.uncached.grant.bits.payload.client_xact_id := io.mem.resp.bits.tag
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io.uncached.grant.bits.payload.master_xact_id := UFix(0) // DNC
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io.uncached.grant.bits.payload.g_type := UFix(0) // DNC
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io.mem.req_cmd <> mem_cmd_q.io.deq
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io.mem.req_data <> mem_data_q.io.deq
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}
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object TileToCrossbarShim {
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def apply[T <: Data](logIO: ClientSourcedIO[LogicalNetworkIO[T]])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = {
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@ -197,7 +314,7 @@ class ReferenceChipBackend extends VerilogBackend
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transforms += ((c: Component) => addMemPin(c))
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}
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class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit conf: CoherenceHubConfiguration) extends Component
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class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
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{
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implicit val lnconf = conf.ln
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val io = new Bundle {
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@ -214,35 +331,31 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
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val lnWithHtifConf = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1,
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idBits = log2Up(conf.ln.nEndpoints+1)+1,
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nClients = conf.ln.nClients+1)
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val chWithHtifConf = conf.copy(ln = lnWithHtifConf)
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require(tileEndpoints.length == lnWithHtifConf.nClients)
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//val hub = new CoherenceHubBroadcast()(chWithHtifConf)
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val ucWithHtifConf = conf.copy(ln = lnWithHtifConf)
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require(clientEndpoints.length == lnWithHtifConf.nClients)
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val masterEndpoints = (0 until lnWithHtifConf.nMasters).map(new L2CoherenceAgent(_)(ucWithHtifConf))
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val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
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val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
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val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
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//val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES)
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val mem_serdes = new MemSerdes(htif_width)
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//val hub = new CoherenceHubBroadcast()(chWithHtifConf)
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//val adapter = new CoherenceHubAdapter()(lnWithHtifConf)
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val hub = new L2CoherenceAgent()(chWithHtifConf)
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val net = new ReferenceChipCrossbarNetwork(List(hub)++tileEndpoints)(lnWithHtifConf)
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//net.io(0) <> adapter.io.net
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//hub.io.tiles <> adapter.io.hub
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hub.io.network <> net.io(0)
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val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)(lnWithHtifConf)
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net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
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masterEndpoints.map{ _.io.incoherent zip (io.incoherent ++ List(Bool(true))) map { case (m, c) => m := c } }
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for (i <- 1 to conf.ln.nClients) {
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net.io(i) <> io.tiles(i-1)
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//hub.io.tiles(i-1) <> io.tiles(i-1)
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hub.io.incoherent(i-1) := io.incoherent(i-1)
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val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
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if(lnWithHtifConf.nMasters > 1) {
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val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters)(lnWithHtifConf)
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arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
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conv.io.uncached <> arb.io.out
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} else {
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conv.io.uncached <> masterEndpoints.head.io.master
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}
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net.io(conf.ln.nClients+1) <> io.htif
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//hub.io.tiles(conf.ln.nClients) <> io.htif
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hub.io.incoherent(conf.ln.nClients) := Bool(true)
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llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd)
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llc.io.cpu.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES)
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hub.io.mem.resp <> llc.io.cpu.resp
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llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd)
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llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, REFILL_CYCLES)
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conv.io.mem.resp <> llc.io.cpu.resp
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// mux between main and backup memory ports
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val mem_cmdq = (new Queue(2)) { new MemReqCmd }
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@ -267,7 +380,7 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
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io.mem_backup <> mem_serdes.io.narrow
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}
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class Uncore(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit conf: CoherenceHubConfiguration) extends Component
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class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
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{
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implicit val lnconf = conf.ln
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val io = new Bundle {
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@ -280,17 +393,38 @@ class Uncore(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit
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val htif = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients) }.flip
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val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
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}
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val nBanks = 1
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val bankIdLsb = 5
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val htif = new rocketHTIF(htif_width)
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val outmemsys = new OuterMemorySystem(htif_width, tileList :+ htif)
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htif.io.cpu <> io.htif
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val outmemsys = new OuterMemorySystem(htif_width, tileEndpoints++List(htif))
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outmemsys.io.tiles <> io.tiles
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outmemsys.io.htif <> htif.io.mem
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outmemsys.io.incoherent <> io.incoherent
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io.mem <> outmemsys.io.mem
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outmemsys.io.mem_backup_en <> io.mem_backup_en
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// Add networking headers and endpoint queues
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(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
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case ((outer, client), i) =>
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val (acq_w_header, acq_data_w_header) = TileLinkHeaderAppender(client.acquire, client.acquire_data, i, nBanks, bankIdLsb)
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outer.acquire <> acq_w_header
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outer.acquire_data <> acq_data_w_header
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val (rel_w_header, rel_data_w_header) = TileLinkHeaderAppender(client.release, client.release_data, i, nBanks, bankIdLsb)
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outer.release <> rel_w_header
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outer.release_data <> rel_data_w_header
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val grant_ack_q = Queue(client.grant_ack)
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outer.grant_ack.valid := grant_ack_q.valid
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outer.grant_ack.bits := grant_ack_q.bits
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outer.grant_ack.bits.header.src := UFix(i)
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grant_ack_q.ready := outer.grant_ack.ready
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client.abort <> Queue(outer.abort)
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.probe <> Queue(outer.probe)
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}
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// pad out the HTIF using a divided clock
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val hio = (new SlowIO(512)) { Bits(width = htif_width+1) }
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hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63
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@ -332,6 +466,7 @@ class TopIO(htif_width: Int) extends Bundle {
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object DummyTopLevelConstants extends _root_.uncore.constants.CoherenceConfigConstants {
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val NTILES = 2
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val NBANKS = 2
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val HTIF_WIDTH = 16
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val ENABLE_SHARING = true
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val ENABLE_CLEAN_EXCLUSIVE = true
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@ -354,8 +489,8 @@ class Top extends Component {
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else new MICoherence
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}
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implicit val lnConf = LogicalNetworkConfiguration(NTILES+1, log2Up(NTILES)+1, 1, NTILES)
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implicit val chConf = CoherenceHubConfiguration(co, lnConf)
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implicit val lnConf = LogicalNetworkConfiguration(NTILES+NBANKS, log2Up(NTILES)+1, NBANKS, NTILES)
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implicit val uConf = UncoreConfiguration(co, lnConf)
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val io = new TopIO(HTIF_WIDTH)
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@ -376,49 +511,14 @@ class Top extends Component {
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resetSigs(i) := hl.reset
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val tile = tileList(i)
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tile.io.tilelink <> tl
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il := hl.reset
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tile.io.host.reset := Reg(Reg(hl.reset))
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tile.io.host.pcr_req <> Queue(hl.pcr_req)
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hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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error_mode = error_mode || Reg(tile.io.host.debug.error_mode)
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val x_init_q = Queue(tile.io.tilelink.acquire)
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tl.acquire.valid := x_init_q.valid
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tl.acquire.bits.payload := x_init_q.bits.payload
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tl.acquire.bits.header.src := UFix(i)
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tl.acquire.bits.header.dst := UFix(0)
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x_init_q.ready := tl.acquire.ready
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val x_init_data_q = Queue(tile.io.tilelink.acquire_data)
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tl.acquire_data.valid := x_init_data_q.valid
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tl.acquire_data.bits.payload := x_init_data_q.bits.payload
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tl.acquire_data.bits.header.src := UFix(i)
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tl.acquire_data.bits.header.dst := UFix(0)
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x_init_data_q.ready := tl.acquire_data.ready
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val x_finish_q = Queue(tile.io.tilelink.grant_ack)
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tl.grant_ack.valid := x_finish_q.valid
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tl.grant_ack.bits.payload := x_finish_q.bits.payload
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tl.grant_ack.bits.header.src := UFix(i)
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tl.grant_ack.bits.header.dst := UFix(0)
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x_finish_q.ready := tl.grant_ack.ready
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val p_rep_q = Queue(tile.io.tilelink.release, 1)
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tl.release.valid := p_rep_q.valid
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tl.release.bits.payload := p_rep_q.bits.payload
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tl.release.bits.header.src := UFix(i)
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tl.release.bits.header.dst := UFix(0)
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p_rep_q.ready := tl.release.ready
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val p_rep_data_q = Queue(tile.io.tilelink.release_data)
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tl.release_data.valid := p_rep_data_q.valid
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tl.release_data.bits.payload := p_rep_data_q.bits.payload
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tl.release_data.bits.header.src := UFix(i)
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tl.release_data.bits.header.dst := UFix(0)
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p_rep_data_q.ready := tl.release_data.ready
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tile.io.tilelink.grant <> Queue(tl.grant, 1, pipe = true)
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tile.io.tilelink.probe <> Queue(tl.probe)
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il := hl.reset
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}
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io.host <> uncore.io.host
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@ -6,7 +6,7 @@ import uncore._
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import rocket._
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import rocket.Constants._
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class FPGAUncore(htif_width: Int)(implicit conf: CoherenceHubConfiguration) extends Component
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class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
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{
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val io = new Bundle {
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val host = new HostIO(htif_width)
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@ -20,16 +20,29 @@ class FPGAUncore(htif_width: Int)(implicit conf: CoherenceHubConfiguration) exte
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htif.io.cpu <> io.htif
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io.host <> htif.io.host
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val lnWithHtif = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1, nClients = conf.ln.nClients+1)
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val hub = new CoherenceHubBroadcast()(conf.copy(ln = lnWithHtif))
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for (i <- 0 until conf.ln.nClients)
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hub.io.tiles(i) <> io.tiles(i)
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hub.io.tiles(conf.ln.nClients) <> htif.io.mem
|
||||
hub.io.incoherent <> io.incoherent
|
||||
val lnWithHtifConf = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1,
|
||||
idBits = log2Up(conf.ln.nEndpoints+1)+1,
|
||||
nClients = conf.ln.nClients+1)
|
||||
val ucWithHtifConf = conf.copy(ln = lnWithHtifConf)
|
||||
val clientEndpoints = tileList :+ htif
|
||||
val masterEndpoints = List.fill(lnWithHtifConf.nMasters)(new L2CoherenceAgent(0)(ucWithHtifConf))
|
||||
|
||||
io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
|
||||
io.mem.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES*2)
|
||||
hub.io.mem.resp <> Queue(io.mem.resp, REFILL_CYCLES*2)
|
||||
val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)(lnWithHtifConf)
|
||||
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
|
||||
masterEndpoints.map{ _.io.incoherent zip (io.incoherent ++ List(Bool(true))) map { case (m, c) => m := c } }
|
||||
|
||||
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
|
||||
if(lnWithHtifConf.nMasters > 1) {
|
||||
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters)(lnWithHtifConf)
|
||||
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
|
||||
conv.io.uncached <> arb.io.out
|
||||
} else {
|
||||
conv.io.uncached <> masterEndpoints.head.io.master
|
||||
}
|
||||
|
||||
io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
|
||||
io.mem.req_data <> Queue(conv.io.mem.req_data, REFILL_CYCLES*2)
|
||||
conv.io.mem.resp <> Queue(io.mem.resp, REFILL_CYCLES*2)
|
||||
}
|
||||
|
||||
class FPGATop extends Component {
|
||||
@ -41,8 +54,7 @@ class FPGATop extends Component {
|
||||
}
|
||||
val co = new MESICoherence
|
||||
implicit val lnConf = LogicalNetworkConfiguration(4, 3, 1, 3)
|
||||
implicit val uconf = CoherenceHubConfiguration(co, lnConf)
|
||||
val uncore = new FPGAUncore(htif_width = htif_width)
|
||||
implicit val uconf = UncoreConfiguration(co, lnConf)
|
||||
|
||||
val resetSigs = Vec(uconf.ln.nClients){ Bool() }
|
||||
val ic = ICacheConfig(64, 1, co, ntlb = 4, nbtb = 4)
|
||||
@ -52,6 +64,7 @@ class FPGATop extends Component {
|
||||
fastMulDiv = false,
|
||||
fpu = false, vec = false)
|
||||
val tileList = (0 until uconf.ln.nClients).map(r => new Tile(resetSignal = resetSigs(r))(rc))
|
||||
val uncore = new FPGAUncore(htif_width = htif_width, tileList = tileList)
|
||||
|
||||
io.debug.error_mode := Bool(false)
|
||||
for (i <- 0 until uconf.ln.nClients) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user