Revert "shuffled FPU control logic around to make functional unit retiming work better"
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
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6275e009f8
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@ -370,8 +370,8 @@ class FPToFP(val latency: Int) extends Component
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class ioFMA(width: Int) extends Bundle {
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val valid = Bool(INPUT)
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val cmd = Bits(INPUT, 2)
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val rm = Bits(INPUT, 2)
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val cmd = Bits(INPUT, FCMD_WIDTH)
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val rm = Bits(INPUT, 3)
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val in1 = Bits(INPUT, width)
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val in2 = Bits(INPUT, width)
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val in3 = Bits(INPUT, width)
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@ -382,126 +382,82 @@ class ioFMA(width: Int) extends Bundle {
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class FPUSFMAPipe(val latency: Int) extends Component
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{
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val io = new ioFMA(33)
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val cmd = Reg() { Bits() }
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val rm = Reg() { Bits() }
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val in1 = Reg() { Bits() }
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val in2 = Reg() { Bits() }
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val in3 = Reg() { Bits() }
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val r_cmd = Reg() { Bits() }
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val r_rm = Reg() { Bits() }
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val r_in1 = Reg() { Bits() }
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val r_in2 = Reg() { Bits() }
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val r_in3 = Reg() { Bits() }
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val out_reg = Reg() { Bits() }
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val exc_reg = Reg() { Bits() }
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val valid_pipe_regs = Vec(latency) { Reg() { Bool() } }
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val dout_pipe_regs = Vec(latency-2) { Reg() { Bits() } }
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val exc_pipe_regs = Vec(latency-2) { Reg() { Bits() } }
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valid_pipe_regs(0) := io.valid
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for (i <- 1 until latency) {
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valid_pipe_regs(i) := valid_pipe_regs(i-1)
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}
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val cmd_fma = io.cmd === FCMD_MADD || io.cmd === FCMD_MSUB ||
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io.cmd === FCMD_NMADD || io.cmd === FCMD_NMSUB
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val cmd_addsub = io.cmd === FCMD_ADD || io.cmd === FCMD_SUB
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val one = Bits("h80000000")
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val zero = Cat(io.in1(32) ^ io.in2(32), Bits(0, 32))
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val valid = Reg(io.valid)
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when (io.valid) {
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r_cmd := io.cmd
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r_rm := io.rm
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r_in1 := io.in1
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r_in2 := io.in2
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r_in3 := io.in3
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cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0))
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rm := io.rm
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in1 := io.in1
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in2 := Mux(cmd_addsub, one, io.in2)
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in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, zero))
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}
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val fma = new hardfloat.mulAddSubRecodedFloatN(23, 9)
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fma.io.op := r_cmd
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fma.io.roundingMode := r_rm
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fma.io.a := r_in1
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fma.io.b := r_in2
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fma.io.c := r_in3
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fma.io.op := cmd
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fma.io.roundingMode := rm
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fma.io.a := in1
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fma.io.b := in2
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fma.io.c := in3
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when (valid_pipe_regs(0)) {
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dout_pipe_regs(0) := fma.io.out
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exc_pipe_regs(0) := fma.io.exceptionFlags
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}
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for (i <- 1 until latency-2) {
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when (valid_pipe_regs(i)) {
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dout_pipe_regs(i) := dout_pipe_regs(i-1)
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exc_pipe_regs(i) := exc_pipe_regs(i-1)
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}
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}
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when (valid_pipe_regs(latency-2)) {
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out_reg := dout_pipe_regs(latency-3)
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exc_reg := exc_pipe_regs(latency-3)
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}
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io.out := out_reg
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io.exc := exc_reg
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io.out := Pipe(valid, fma.io.out, latency-1).bits
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io.exc := Pipe(valid, fma.io.exceptionFlags, latency-1).bits
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}
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class FPUDFMAPipe(val latency: Int) extends Component
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{
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val io = new ioFMA(65)
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val r_cmd = Reg() { Bits() }
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val r_rm = Reg() { Bits() }
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val r_in1 = Reg() { Bits() }
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val r_in2 = Reg() { Bits() }
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val r_in3 = Reg() { Bits() }
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val out_reg = Reg() { Bits() }
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val exc_reg = Reg() { Bits() }
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val valid_pipe_regs = Vec(latency) { Reg() { Bool() } }
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val dout_pipe_regs = Vec(latency-2) { Reg() { Bits() } }
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val exc_pipe_regs = Vec(latency-2) { Reg() { Bits() } }
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valid_pipe_regs(0) := io.valid
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for (i <- 1 until latency) {
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valid_pipe_regs(i) := valid_pipe_regs(i-1)
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}
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val cmd = Reg() { Bits() }
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val rm = Reg() { Bits() }
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val in1 = Reg() { Bits() }
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val in2 = Reg() { Bits() }
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val in3 = Reg() { Bits() }
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val cmd_fma = io.cmd === FCMD_MADD || io.cmd === FCMD_MSUB ||
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io.cmd === FCMD_NMADD || io.cmd === FCMD_NMSUB
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val cmd_addsub = io.cmd === FCMD_ADD || io.cmd === FCMD_SUB
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val one = Bits("h8000000000000000")
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val zero = Cat(io.in1(64) ^ io.in2(64), Bits(0, 64))
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val valid = Reg(io.valid)
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when (io.valid) {
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r_cmd := io.cmd
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r_rm := io.rm
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r_in1 := io.in1
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r_in2 := io.in2
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r_in3 := io.in3
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cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0))
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rm := io.rm
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in1 := io.in1
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in2 := Mux(cmd_addsub, one, io.in2)
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in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, zero))
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}
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val fma = new hardfloat.mulAddSubRecodedFloatN(52, 12)
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fma.io.op := r_cmd
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fma.io.roundingMode := r_rm
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fma.io.a := r_in1
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fma.io.b := r_in2
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fma.io.c := r_in3
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fma.io.op := cmd
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fma.io.roundingMode := rm
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fma.io.a := in1
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fma.io.b := in2
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fma.io.c := in3
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when (valid_pipe_regs(0)) {
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dout_pipe_regs(0) := fma.io.out
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exc_pipe_regs(0) := fma.io.exceptionFlags
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}
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for (i <- 1 until latency-2) {
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when (valid_pipe_regs(i)) {
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dout_pipe_regs(i) := dout_pipe_regs(i-1)
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exc_pipe_regs(i) := exc_pipe_regs(i-1)
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}
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}
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when (valid_pipe_regs(latency-2)) {
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out_reg := dout_pipe_regs(latency-3)
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exc_reg := exc_pipe_regs(latency-3)
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}
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io.out := out_reg
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io.exc := exc_reg
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io.out := Pipe(valid, fma.io.out, latency-1).bits
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io.exc := Pipe(valid, fma.io.exceptionFlags, latency-1).bits
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}
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class FPU(sfma_latency: Int, dfma_latency: Int) extends Component
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{
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val io = new Bundle {
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val ctrl = new CtrlFPUIO().flip
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val dpath = new DpathFPUIO().flip
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val ctrl = (new CtrlFPUIO).flip
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val dpath = (new DpathFPUIO).flip
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val sfma = new ioFMA(33)
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val dfma = new ioFMA(65)
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}
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@ -570,52 +526,23 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Component
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val cmd_fma = mem_ctrl.cmd === FCMD_MADD || mem_ctrl.cmd === FCMD_MSUB ||
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mem_ctrl.cmd === FCMD_NMADD || mem_ctrl.cmd === FCMD_NMSUB
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val cmd_addsub = mem_ctrl.cmd === FCMD_ADD || mem_ctrl.cmd === FCMD_SUB
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// RIMAS: refactoring for retiming
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// moved recoding of cmd -> op outside of DFMA/SFMA blocks
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// also moved muxing of operands based on command bits out of module
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// Single precision FMA
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val sfma = new FPUSFMAPipe(sfma_latency)
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val sfma_cmd = Mux(io.sfma.valid, io.sfma.cmd, ctrl.cmd)
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val sfma_cmd_fma = sfma_cmd === FCMD_MADD || sfma_cmd === FCMD_MSUB ||
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sfma_cmd === FCMD_NMADD || sfma_cmd === FCMD_NMSUB
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val sfma_cmd_addsub = sfma_cmd === FCMD_ADD || sfma_cmd === FCMD_SUB
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val sfma_in1 = Mux(io.sfma.valid, io.sfma.in1, ex_rs1)
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val sfma_in2 = Mux(io.sfma.valid, io.sfma.in2, ex_rs2)
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val sfma_in3 = Mux(io.sfma.valid, io.sfma.in3, ex_rs3)
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val sfma_one = Bits("h80000000")
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val sfma_zero = Cat(sfma_in1(32) ^ sfma_in2(32), Bits(0, 32))
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sfma.io.valid := io.sfma.valid || ex_reg_valid && ctrl.fma && ctrl.single
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sfma.io.in1 := sfma_in1
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sfma.io.in2 := Mux(sfma_cmd_addsub, sfma_one, sfma_in2)
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sfma.io.in3 := Mux(sfma_cmd_fma, sfma_in3, Mux(sfma_cmd_addsub, sfma_in2, sfma_zero))
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sfma.io.cmd := Cat(sfma_cmd(1) & (sfma_cmd_fma || sfma_cmd_addsub), sfma_cmd(0))
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sfma.io.rm := Mux(io.sfma.valid, io.sfma.rm(1,0), ex_rm(1,0))
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sfma.io.in1 := Mux(io.sfma.valid, io.sfma.in1, ex_rs1)
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sfma.io.in2 := Mux(io.sfma.valid, io.sfma.in2, ex_rs2)
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sfma.io.in3 := Mux(io.sfma.valid, io.sfma.in3, ex_rs3)
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sfma.io.cmd := Mux(io.sfma.valid, io.sfma.cmd, ctrl.cmd)
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sfma.io.rm := Mux(io.sfma.valid, io.sfma.rm, ex_rm)
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io.sfma.out := sfma.io.out
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io.sfma.exc := sfma.io.exc
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// Double precision FMA
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val dfma = new FPUDFMAPipe(dfma_latency)
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val dfma_cmd = Mux(io.dfma.valid, io.dfma.cmd, ctrl.cmd)
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val dfma_cmd_fma = dfma_cmd === FCMD_MADD || dfma_cmd === FCMD_MSUB ||
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dfma_cmd === FCMD_NMADD || dfma_cmd === FCMD_NMSUB
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val dfma_cmd_addsub = dfma_cmd === FCMD_ADD || dfma_cmd === FCMD_SUB
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val dfma_in1 = Mux(io.dfma.valid, io.dfma.in1, ex_rs1)
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val dfma_in2 = Mux(io.dfma.valid, io.dfma.in2, ex_rs2)
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val dfma_in3 = Mux(io.dfma.valid, io.dfma.in3, ex_rs3)
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val dfma_one = Bits("h8000000000000000")
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val dfma_zero = Cat(dfma_in1(64) ^ dfma_in2(64), Bits(0, 64))
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dfma.io.valid := io.dfma.valid || ex_reg_valid && ctrl.fma && !ctrl.single
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dfma.io.in1 := dfma_in1
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dfma.io.in2 := Mux(dfma_cmd_addsub, dfma_one, dfma_in2)
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dfma.io.in3 := Mux(dfma_cmd_fma, dfma_in3, Mux(dfma_cmd_addsub, dfma_in2, dfma_zero))
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dfma.io.cmd := Cat(dfma_cmd(1) & (dfma_cmd_fma || dfma_cmd_addsub), dfma_cmd(0))
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dfma.io.rm := Mux(io.dfma.valid, io.dfma.rm(1,0), ex_rm(1,0))
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dfma.io.in1 := Mux(io.dfma.valid, io.dfma.in1, ex_rs1)
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dfma.io.in2 := Mux(io.dfma.valid, io.dfma.in2, ex_rs2)
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dfma.io.in3 := Mux(io.dfma.valid, io.dfma.in3, ex_rs3)
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dfma.io.cmd := Mux(io.dfma.valid, io.dfma.cmd, ctrl.cmd)
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dfma.io.rm := Mux(io.dfma.valid, io.dfma.rm, ex_rm)
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io.dfma.out := dfma.io.out
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io.dfma.exc := dfma.io.exc
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