1
0
Commit Graph

1138 Commits

Author SHA1 Message Date
Andrew Waterman
661f8e635b merge I$, ITLB, BTB into Frontend 2012-10-16 02:24:37 -07:00
Andrew Waterman
fcd69dba98 add optional early-out to mul/div 2012-10-16 02:24:37 -07:00
Andrew Waterman
27ddff1adb simplify and improve multiplier 2012-10-16 02:24:37 -07:00
Henry Cook
8970b635b2 improvements to implicit RocketConfiguration parameter 2012-10-15 16:29:49 -07:00
Henry Cook
a7a4e65690 Initial verison of reading config from files 2012-10-15 16:05:50 -07:00
Henry Cook
5d2a470215 all rocket-specific arbiters in one file and refactored traits slightly 2012-10-15 16:05:32 -07:00
Huy Vo
1864e41361 memserdes + slowio out of rocket and into uncore 2012-10-10 15:25:24 -07:00
Huy Vo
fe21142972 fixed memdessert unpacking 2012-10-09 13:03:17 -07:00
Henry Cook
9025d0610c first pass at configuration object passed as implicit parameter 2012-10-07 22:37:29 -07:00
Henry Cook
dfdfddebe8 constants as traits 2012-10-07 22:20:03 -07:00
Henry Cook
b5ff436092 decode constant object split into multiple objects 2012-10-05 15:50:42 -07:00
Andrew Waterman
ed8cc4a1cf eliminate D$ probe->WB critical path 2012-10-04 09:05:14 -07:00
Huy Vo
e909093f37 factoring out uncore into separate uncore repo 2012-10-01 16:08:41 -07:00
Henry Cook
b9a9664de5 uncore and rocket changes for new xact types 2012-10-01 10:47:36 -07:00
Huy Vo
d9cb96c0ae factored out common stuff to ChiselUtil 2012-09-27 22:53:34 -07:00
Andrew Waterman
667b4ee858 remove Queue flush port (override reset instead) 2012-08-22 13:39:19 -07:00
Andrew Waterman
d4a001b867 add PriorityMux; use to implement PriorityEncoder 2012-08-22 13:38:25 -07:00
Andrew Waterman
743e032f06 generalize interface to DecodeLogic 2012-08-22 13:38:07 -07:00
Andrew Waterman
0f20771664 rename queue to Queue
fixes build with case-insensitive file system
2012-08-08 22:11:59 -07:00
Andrew Waterman
897a4e349b fix some LLC control bugs 2012-08-06 17:10:04 -07:00
Andrew Waterman
e9c35b4923 ameliorate DTLB kill->rdy critical path 2012-08-06 17:05:05 -07:00
Andrew Waterman
b94e6915ab refactor IPIs; use new tohost/fromhost protocol 2012-08-03 19:00:34 -07:00
Andrew Waterman
6510f020c7 fix deadlock in coherence hub 2012-08-03 19:00:03 -07:00
Andrew Waterman
e3726c4db0 fix control bug in LLC
structural hazard on tag ram caused deadlock
2012-08-03 18:59:37 -07:00
Andrew Waterman
def913096e pipeline LLC further 2012-07-31 17:45:14 -07:00
Andrew Waterman
3a8f3e0de5 further pipeline the LLC 2012-07-30 20:12:11 -07:00
Andrew Waterman
80c243469e add flow queues and skid buffers
hopefully they work
2012-07-30 18:47:12 -07:00
Andrew Waterman
be4fa936dd fix PriorityEncoderOH bug 2012-07-30 18:28:54 -07:00
Andrew Waterman
2ec76390e3 improve PriorityEncoderOH and add Counter util 2012-07-30 16:06:55 -07:00
Yunsup Lee
2af84f994a remove reset pin on llc 2012-07-28 21:14:51 -07:00
Yunsup Lee
0a1cd1175c add reset pin to llc 2012-07-27 18:44:39 -07:00
Huy Vo
db91c4cf6c hwacha 2012-07-27 18:13:20 -07:00
Huy Vo
32a16d183f consts file doesn't depend on WIDTH_PVFB if HAVE_PVFB == false 2012-07-27 18:13:20 -07:00
Andrew Waterman
130fa95ed6 expand HTIF's PCR register space 2012-07-27 14:52:39 -07:00
Andrew Waterman
7778802395 reduce number of outstanding transactions 2012-07-26 14:51:41 -07:00
Andrew Waterman
9c50621a19 remove chip-specific uncore gunk 2012-07-26 03:26:52 -07:00
Andrew Waterman
a5bea4364f memory system bug fixes 2012-07-26 00:05:21 -07:00
Yunsup Lee
3a2b305ddf change htif width to 16 2012-07-25 17:25:50 -07:00
Andrew Waterman
177dbdadd9 merge HTIF port and backup memory port 2012-07-25 00:18:02 -07:00
Yunsup Lee
309193dd07 change llc size 2012-07-24 14:10:29 -07:00
Yunsup Lee
6541cf22a4 fix bug in coherence hub, respect xact_rep.ready 2012-07-23 20:56:55 -07:00
Yunsup Lee
f4e3e72ad1 hoist HTIF_WIDTH out to consts 2012-07-23 17:30:04 -07:00
Andrew Waterman
a21c355114 fix htif split request/response 2012-07-23 17:15:16 -07:00
Andrew Waterman
938effc053 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Yunsup Lee
379f021359 change ioHTIF interface between the tile/uncore boundary to cope with asynchrony 2012-07-22 18:26:02 -07:00
Yunsup Lee
c892950bf1 hoist out uncore as its own component 2012-07-22 17:48:17 -07:00
Huy Vo
0a97d6ab4d type casting 2012-07-18 13:03:35 -07:00
Andrew Waterman
f42c6afed2 decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
2012-07-17 22:55:40 -07:00
Andrew Waterman
4e44ed7400 allow back pressure on IPI requests 2012-07-17 22:55:40 -07:00
Yunsup Lee
f633a55722 fix dcache tag array size 2012-07-16 22:19:03 -07:00