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6cde69e95d
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Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
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2013-09-09 14:31:18 -07:00 |
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cfbfa6b895
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Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
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2013-09-05 19:22:34 -07:00 |
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e23e8e3850
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/memserdes.scala
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2013-09-05 16:17:34 -07:00 |
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d896ccbd43
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
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2013-09-05 16:11:53 -07:00 |
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f27c0fb010
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Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2
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2013-09-05 15:01:56 -07:00 |
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69daae0dae
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Add dependency resolvers to build.scala to fix build script
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2013-09-05 14:56:41 -07:00 |
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2c47b4388a
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push rocket
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2013-08-26 14:54:49 -07:00 |
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b9f6e1a7ec
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Don't update BTB when garbage was fetched
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2013-08-26 14:53:04 -07:00 |
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9003bc2614
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push rocket
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2013-08-24 22:42:57 -07:00 |
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44e92edf92
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fix scr parameterization bug
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2013-08-24 22:42:51 -07:00 |
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d0674af13f
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forgot to push riscv-rocket
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2013-08-24 22:15:38 -07:00 |
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3895b75a56
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Support non-power-of-2 BTBs; prefer invalid entries
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2013-08-24 17:33:11 -07:00 |
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ba9bbc27df
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apply same change to fpga top-level
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2013-08-24 15:50:03 -07:00 |
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76cd90fc01
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parameterize number of SCRs
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2013-08-24 15:47:42 -07:00 |
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2ca5127785
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parameterize number of SCRs
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2013-08-24 15:47:14 -07:00 |
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694ebd65cf
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push uncore
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2013-08-24 15:24:25 -07:00 |
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b01fe4f6aa
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fix memserdes bit ordering
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2013-08-24 15:24:17 -07:00 |
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daf23b8f79
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Add early out to multiplier
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2013-08-24 14:44:23 -07:00 |
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67f80ba4b2
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Stall div/mul writeback until WB slot is free
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2013-08-24 14:44:17 -07:00 |
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d1b5076fee
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Don't update BTB when garbage was fetched
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2013-08-24 14:44:11 -07:00 |
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52e31f3298
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Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
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2013-08-24 14:44:04 -07:00 |
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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0884bc9789
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fix DRAMSideLLCNull entries
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2013-08-24 13:20:38 -07:00 |
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1e3ac0afa9
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back to NTILES=1
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2013-08-24 13:10:30 -07:00 |
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9aff60f340
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whitespace error in build.sbt
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2013-08-21 16:16:42 -07:00 |
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dc53529156
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added resolver, bumped chisel dependency
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2013-08-21 16:00:51 -07:00 |
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6aa500fc16
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dont make assumptions about default project name when invoking sbt
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2013-08-20 12:56:01 -07:00 |
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b06d33da2f
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Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
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2013-08-19 19:54:41 -07:00 |
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ff7b486006
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standardized sbt build
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2013-08-15 18:13:19 -07:00 |
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85e5ce046f
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pulled submodule commits, uncore sbt standardized
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2013-08-15 17:07:13 -07:00 |
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6b20556661
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Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2
Conflicts:
chisel
riscv-hwacha
riscv-rocket
uncore
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2013-08-15 16:39:30 -07:00 |
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784e017bae
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Final Reg standardization
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2013-08-15 16:37:58 -07:00 |
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ae02ebd153
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Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
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2013-08-15 16:35:27 -07:00 |
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b80f45f8f2
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Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2
Conflicts:
src/main/scala/llc.scala
src/main/scala/slowio.scala
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2013-08-15 16:22:12 -07:00 |
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3763cd0004
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standardizing sbt build conventions
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2013-08-15 15:57:16 -07:00 |
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
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17d404b325
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final Reg changes
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2013-08-15 15:27:38 -07:00 |
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9b70ecf546
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Reg standardization
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2013-08-13 17:53:19 -07:00 |
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1308c08baa
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Reg standardization
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2013-08-13 17:52:53 -07:00 |
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
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7ff4126d04
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Abstracted UncachedTileLinkIOArbiters
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2013-08-13 00:01:11 -07:00 |
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9162fbc9b5
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Clean up cloning in tilelink bundles
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2013-08-12 23:15:54 -07:00 |
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858169917e
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removed dummy DNCs handled by pruning
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2013-08-12 22:34:46 -07:00 |
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d9b3c7cfc8
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Moved RenEn to ChiselUtil
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2013-08-12 22:18:25 -07:00 |
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d7d13255db
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chisel tag
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2013-08-12 20:53:29 -07:00 |
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f9d1403a92
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tags
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2013-08-12 20:53:17 -07:00 |
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cc6631ae4d
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reset -> _reset
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2013-08-12 20:52:55 -07:00 |
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d5c9eb0f54
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reset -> resetVal, getReset -> reset
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2013-08-12 20:52:18 -07:00 |
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387cf0ebe0
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reset -> resetVal, getReset -> reset
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2013-08-12 20:51:54 -07:00 |
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11e131af47
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initial attempt at upgrade
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2013-08-12 10:46:22 -07:00 |
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