Henry Cook
|
c03976896e
|
separate queues for resp tag and data
|
2015-03-15 17:58:17 -07:00 |
|
Andrew Waterman
|
6e540825b2
|
Use entire 12-bit CSR address
|
2015-03-14 02:15:24 -07:00 |
|
Yunsup Lee
|
3a78ca210d
|
bugfix in uncached TL to TL convertors
|
2015-03-12 16:33:41 -07:00 |
|
Henry Cook
|
8181262419
|
clean up incoherent and probe flags
|
2015-03-12 16:22:14 -07:00 |
|
Henry Cook
|
dcc84c4dd3
|
arbiter probe ready bugfix
|
2015-03-12 16:02:51 -07:00 |
|
Yunsup Lee
|
2c31ed6426
|
previous bug fix for meta data writeback wasn't quite right
|
2015-03-12 15:34:20 -07:00 |
|
Yunsup Lee
|
5e40c8ba77
|
write back meta data when cache miss even when coherence meta data is clean
|
2015-03-12 14:36:46 -07:00 |
|
Albert Ou
|
8f8022379c
|
Fix AMO opcode extraction
|
2015-03-11 23:24:58 -07:00 |
|
Albert Ou
|
f75126c39c
|
Require self probes for all built-in Acquire types
This ensures that puts by the RoCC accelerator properly invalidates its
tile's L1 D$, with which it currently shares the same TileLink port.
|
2015-03-11 23:24:58 -07:00 |
|
Henry Cook
|
1aff919c24
|
added prefetchAck Grant type
|
2015-03-11 17:32:06 -07:00 |
|
Henry Cook
|
059575c334
|
cleanup mergeData and prep for cleaner data_buffer in L2
|
2015-03-11 15:43:41 -07:00 |
|
Henry Cook
|
b4ed1d9121
|
Add builtin prefetch types to TileLink
|
2015-03-11 14:28:17 -07:00 |
|
Yunsup Lee
|
3ab1aca7de
|
L2 subblock access bugfix
|
2015-03-11 01:56:47 -07:00 |
|
Henry Cook
|
17072a0041
|
L2 Writeback bugfix
|
2015-03-10 01:15:03 -07:00 |
|
Henry Cook
|
a1f04386f7
|
Headerless TileLinkIO and arbiters
|
2015-03-09 16:34:59 -07:00 |
|
Henry Cook
|
002f1a1b39
|
pin outer finish header
|
2015-03-09 12:40:37 -07:00 |
|
Henry Cook
|
df79e7ff8d
|
secondary miss bug
|
2015-03-05 15:51:18 -08:00 |
|
Henry Cook
|
8e41fcf6fc
|
reduce MemIFTag size, enable non pow2 HellaFLowQueue size
|
2015-03-05 15:51:02 -08:00 |
|
Henry Cook
|
1bed6ea498
|
New metadata-based coherence API
|
2015-02-28 17:32:03 -08:00 |
|
Henry Cook
|
0a8722e881
|
bugfix for indexing DataArray of of small L2
|
2015-02-17 00:37:40 -08:00 |
|
Henry Cook
|
0c66e70f14
|
cleanup of conflicts; allocation bugfix
|
2015-02-06 13:20:44 -08:00 |
|
Henry Cook
|
7b86ea17cf
|
rename L2HellaCache to L2HellaCacheBank
|
2015-02-03 19:38:01 -08:00 |
|
Stephen Twigg
|
3b3250339a
|
Explicitely convert results of Bits Muxes to UInt
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
|
2015-02-03 18:15:01 -08:00 |
|
Henry Cook
|
6141b3efc5
|
uncached -> builtin_type
|
2015-02-02 01:02:06 -08:00 |
|
Henry Cook
|
e6491d351f
|
Offset AMOs within beat and return old value
|
2015-02-02 00:22:21 -08:00 |
|
Henry Cook
|
3aa030f960
|
Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
|
2015-02-01 20:37:16 -08:00 |
|
Henry Cook
|
7b4e9dd137
|
Block L2 transactions on the same set from proceeding in parallel
|
2015-02-01 20:29:23 -08:00 |
|
Henry Cook
|
973eb43128
|
state machine bug on uncached write hits
|
2015-02-01 20:29:23 -08:00 |
|
Henry Cook
|
f58f8bf385
|
Make L2 data array use a single Mem
|
2015-01-25 15:37:04 -08:00 |
|
Henry Cook
|
9ef00d187f
|
%s/master/manager/g + better comments
|
2014-12-29 22:55:58 -08:00 |
|
Henry Cook
|
e62c71203e
|
disconnect unused outer network headers
|
2014-12-22 18:50:37 -08:00 |
|
Henry Cook
|
2ef4357ca8
|
acquire allocation bugfix
|
2014-12-19 17:39:23 -08:00 |
|
Henry Cook
|
f234fe65ce
|
Initial verison of L2WritebackUnit, passes MiT2 bmark tests
|
2014-12-19 03:03:53 -08:00 |
|
Henry Cook
|
d121af7f94
|
Simplify release handling
|
2014-12-18 17:12:29 -08:00 |
|
Henry Cook
|
bfcfc3fe18
|
refactor cache params
|
2014-12-17 14:28:14 -08:00 |
|
Henry Cook
|
ab39cbb15d
|
cleanup DirectoryRepresentation and coherence params
|
2014-12-15 19:24:42 -08:00 |
|
Andrew Waterman
|
d04da83f96
|
Make data RAMs 1RW instead of 1R1W
|
2014-12-15 17:36:17 -08:00 |
|
Henry Cook
|
6a8b66231c
|
Add uncached->cached tilelink converter
|
2014-12-12 17:06:03 -08:00 |
|
Henry Cook
|
424df2368f
|
1R/W L2 data array?
Add TLDataBeats to new LLC; all bmarks pass
|
2014-12-12 17:05:21 -08:00 |
|
Henry Cook
|
3026c46a9c
|
Finish adding TLDataBeats to uncore & hub
|
2014-12-12 17:04:52 -08:00 |
|
Henry Cook
|
2f733a60db
|
Begin adding TLDataBeats to uncore
|
2014-12-12 17:04:31 -08:00 |
|
Henry Cook
|
404773eb9f
|
fix wb bug
|
2014-12-03 14:22:39 -08:00 |
|
Henry Cook
|
05b5188ad9
|
meta and data bundle refactor
|
2014-11-19 15:55:25 -08:00 |
|
Henry Cook
|
a519a43f23
|
Merge branch 'master' into new-llc
Conflicts:
src/main/scala/coherence.scala
src/main/scala/memserdes.scala
src/main/scala/tilelink.scala
|
2014-11-12 16:25:25 -08:00 |
|
Henry Cook
|
cb7e712599
|
Added uncached write data queue to coherence hub
|
2014-11-12 12:55:07 -08:00 |
|
Henry Cook
|
82155f333e
|
Major tilelink revision for uncached message types
|
2014-11-11 17:36:55 -08:00 |
|
Henry Cook
|
35553cc0b7
|
NullDirectory sharers.count fix
|
2014-11-11 16:05:25 -08:00 |
|
Henry Cook
|
10309849b7
|
Remove master_xact_id from Probe and Release
|
2014-11-06 12:07:33 -08:00 |
|
Henry Cook
|
27c72e5eed
|
nearly all isa tests pass
|
2014-10-23 21:50:03 -07:00 |
|
Henry Cook
|
a891ba1d46
|
more correct handling of internal state
|
2014-10-21 17:40:30 -07:00 |
|
Henry Cook
|
044b19dbc1
|
Compiles and elaborates, does not pass asm tests
|
2014-10-15 11:46:35 -07:00 |
|
Henry Cook
|
86bdbd6535
|
new tshrs, compiles but does not elaborate
|
2014-10-07 22:33:10 -07:00 |
|
Henry Cook
|
394eb38a96
|
temp; converted voluntary wb tracker
|
2014-10-03 01:06:49 -07:00 |
|
Henry Cook
|
dc1a61264d
|
initial version, acts like old hub
|
2014-10-03 01:06:49 -07:00 |
|
Henry Cook
|
d735f64110
|
Parameter API update
|
2014-10-02 16:47:35 -07:00 |
|
Henry Cook
|
7571695320
|
Removed broken or unfinished modules, new MemPipeIO converter
|
2014-09-24 15:11:24 -07:00 |
|
Henry Cook
|
82fe22f958
|
support for multiple tilelink paramerterizations in same design
Conflicts:
src/main/scala/cache.scala
|
2014-09-24 11:30:40 -07:00 |
|
Henry Cook
|
53b8d7b031
|
use new coherence methods in l2, ready to query dir logic
|
2014-09-20 18:01:14 -07:00 |
|
Henry Cook
|
149d51d644
|
more coherence API cleanup
|
2014-09-20 16:57:13 -07:00 |
|
Henry Cook
|
faed47d131
|
use thunk for dir info
|
2014-09-20 16:54:28 -07:00 |
|
Henry Cook
|
f7b1e23ead
|
functional style on MuxBundle
|
2014-09-20 16:54:28 -07:00 |
|
Yunsup Lee
|
0b51d70bd2
|
add LICENSE
|
2014-09-12 15:31:38 -07:00 |
|
Yunsup Lee
|
f8d450b4e2
|
mark DRAMSideLLC as HasKnownBug
|
2014-09-11 22:06:03 -07:00 |
|
Henry Cook
|
712f3a754d
|
merge in master
|
2014-09-02 12:34:42 -07:00 |
|
Henry Cook
|
17b2359c9a
|
htif parameters trait
|
2014-08-24 19:27:58 -07:00 |
|
Henry Cook
|
dc5643b12f
|
Final parameter refactor.
|
2014-08-23 01:19:36 -07:00 |
|
Henry Cook
|
e26f8a6f6a
|
Fix errors in derived cache params
|
2014-08-12 14:55:44 -07:00 |
|
Henry Cook
|
9ab3a4262c
|
Cache utility traits. Completely compiles, asm tests hang.
|
2014-08-11 18:35:49 -07:00 |
|
Henry Cook
|
f411fdcce3
|
Full conversion to params. Compiles but does not elaborate.
|
2014-08-08 12:21:57 -07:00 |
|
Henry Cook
|
3c329df7e7
|
refactor Metadata, clean and expand coherence API
|
2014-05-28 13:35:08 -07:00 |
|
Andrew Waterman
|
364a6de214
|
Use Mem instead of Vec[Reg]
|
2014-05-18 19:26:35 -07:00 |
|
Henry Cook
|
0e39346a12
|
L2-specific metadataarray wrapper, hookups to tshrfile
|
2014-05-07 01:51:46 -07:00 |
|
Henry Cook
|
bc3ef1011e
|
correct use of function value to initialize MetaDataArray
|
2014-05-06 12:59:45 -07:00 |
|
Henry Cook
|
45172f1f37
|
parameterize metadataarray
|
2014-05-01 01:44:59 -07:00 |
|
Henry Cook
|
0237229921
|
client/master -> inner/outer
|
2014-04-29 16:49:18 -07:00 |
|
Henry Cook
|
52c6de5641
|
DRAMSideLLCLike trait. TSHRFile. New L2 config objects.
|
2014-04-26 19:11:36 -07:00 |
|
Henry Cook
|
1163131d1e
|
TileLinkIO.GrantAck -> TileLinkIO.Finish
|
2014-04-26 15:17:05 -07:00 |
|
Henry Cook
|
3f53d532c2
|
uniquify tilelink conf val name for easier subtyping
|
2014-04-26 14:58:38 -07:00 |
|
Henry Cook
|
f8f29c69b8
|
MetaData & friends moved to uncore/
|
2014-04-23 16:24:20 -07:00 |
|
Henry Cook
|
39681303b8
|
beginning of l2 cache
|
2014-04-22 16:58:15 -07:00 |
|
Henry Cook
|
5613dc7d1b
|
replaced Lists with Vecs
|
2014-04-18 17:26:56 -07:00 |
|
Henry Cook
|
b1df49ba30
|
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
|
2014-04-10 12:35:43 -07:00 |
|
Henry Cook
|
fbca7c6bb3
|
refactor ioMem and associcated constants. merge Aqcuire and AcquireData
|
2014-04-10 12:35:43 -07:00 |
|
Andrew Waterman
|
02dbd6b0aa
|
Don't assign to your own inputs
|
2014-02-12 18:39:40 -08:00 |
|
Henry Cook
|
bbf8010230
|
cleanups supporting uncore hierarchy
|
2014-01-31 15:59:21 -08:00 |
|
Andrew Waterman
|
3e634aef1d
|
Fix HTIF for cache line sizes other than 64 B
|
2014-01-22 18:20:36 -08:00 |
|
Andrew Waterman
|
4f1213cb8b
|
Fix Scala integer overflow
|
2014-01-13 21:45:14 -08:00 |
|
Andrew Waterman
|
acc0d2b06c
|
Only use LSBs for HTIF control regs
For now, at least...
|
2013-11-25 04:34:16 -08:00 |
|
Yunsup Lee
|
056bb156ca
|
make CacheConstants an object
|
2013-11-20 16:43:55 -08:00 |
|
Yunsup Lee
|
f13d76628b
|
forgot to put htif into uncore package
|
2013-11-07 15:42:10 -08:00 |
|
Yunsup Lee
|
c350cbd6ea
|
move htif to uncore
|
2013-11-07 13:19:04 -08:00 |
|
Yunsup Lee
|
f440df5338
|
rename M_FENCE to M_NOP
|
2013-10-28 22:37:41 -07:00 |
|
Huy Vo
|
cc3dc1bd0f
|
bug fix
|
2013-09-19 20:10:56 -07:00 |
|
Andrew Waterman
|
cc7783404d
|
Add memory command M_XA_XOR
|
2013-09-12 16:09:53 -07:00 |
|
Henry Cook
|
1cac26fd76
|
NetworkIOs no longer use thunks
|
2013-09-10 16:15:41 -07:00 |
|
Henry Cook
|
ee98cd8378
|
new enum syntax
|
2013-09-10 10:54:51 -07:00 |
|
Stephen Twigg
|
e23e8e3850
|
Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/memserdes.scala
|
2013-09-05 16:17:34 -07:00 |
|
Henry Cook
|
b80f45f8f2
|
Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2
Conflicts:
src/main/scala/llc.scala
src/main/scala/slowio.scala
|
2013-08-15 16:22:12 -07:00 |
|
Henry Cook
|
3763cd0004
|
standardizing sbt build conventions
|
2013-08-15 15:57:16 -07:00 |
|