The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."
This fixes the following compile warning:
rand_value = $random($urandom);
|
ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
* debug: Clean up Debug TransportModule synchronizer
With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.
I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
* util: Do Set/Reset Async Registers more properly
The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.
This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).
* Tabs, not spaces, in Makefiles
* util: Fix typos in Async BB Reg Comments
- The DebugTransportModuleJtag is written in Verilog. It probably could be written in
Chisel except for some negative edge clocking requirement.
- For real implementations, the AsyncDebugBusTo/From is insufficient. This commit
includes cases where they are used, but because they are not reset asynchronously,
a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false.
- This commit differs significantly from the earlier attempt. Now, the
DTM and synchronizer is instantiated within Top, as it is a real piece of
hardware (vs. test infrastructure).
-TestHarness takes a parameter vs. creating an entirely new TestHarness class.
It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false,
and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM)
is true.
To build Verilog which includes the JtagDTM within Top:
make CONFIG=WithJtagDTM_...
To test using gdb->OpenOCD->jtag_vpi->Verilog:
First, install openocd (included in this commit)
./bootstrap
./configure --prefix=$OPENOCD --enable-jtag-vpi
make
make install
Then to run a simulation:
On a 32-bit core:
$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
--run ./simv-TestHarness-WithJtagDTM_... \
--cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
--freedom-e300-sim \
SimpleRegisterTest.test_s0
On a 64-bit core:
$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
--run ./simv-TestHarness-WithJtagDTM_... \
--cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
--freedom-u500-sim \
SimpleRegisterTest.test_s0
Initial cut
checkpoint which compiles and runs but there is some off-by-1 in the protocol
Debugging the clock crossing logic
checkpoint which works
Clean up the AsyncMailbox black box
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.
This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM. Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.
Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion. This makes a few changes:
* Rather than calling the backup memory port parameters MEM_*, it calls
them MIF_* (to match the MIT* paramater objects). A new name was
necessary because the Nasti stuff is now dumped as MEM_*, which has
similar names but incompatible values.
* p(MIFDataBits) was changed back to 128, as otherwise the backup
memory port doesn't work (it only send half a TileLink transaction).
64 also causes readmemh to bail out, but changing the elf2hex parameters
works around that.
* A configuration was added that enabled the backup memory port in the
tester. While this is kind of an awkward way to do it, I want to
make sure I can start testing this regularly and this makes it easy to
integrate.
