riscv/rocket-chip
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Disable printf/assert during reset

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This commit is contained in:
Andrew Waterman
2016-04-01 16:40:13 -07:00
committed by Henry Cook
parent cd9e07d8e7
commit 46d7dceb1e
3 changed files with 3 additions and 1 deletions
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1
vsrc/ZscaleTestHarness.v
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@ -33,6 +33,7 @@ module ZscaleTestHarness;
reg [ 63:0] max_cycles = 0;
reg [ 63:0] trace_count = 0;
reg verbose = 0;
wire printf_cond = verbose && !reset;
integer stderr = 32'h80000002;
integer i;
reg [127:0] image [8191:0];

1
vsrc/rocketTestHarness.v
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@ -78,6 +78,7 @@ module rocketTestHarness;
reg stats_active = 0;
reg stats_tracking = 0;
reg verbose = 0;
wire printf_cond = verbose && !reset;
integer stderr = 32'h80000002;
`include `TBVFRAG