riscv/rocket-chip
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Get rid of MemIO in Top and replace with AXI throughout

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This commit is contained in:
Howard Mao
2015-10-14 11:33:18 -07:00
parent 032bdd0601
commit 9dabcab9c2
10 changed files with 651 additions and 299 deletions
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315
vsrc/rocketTestHarness.v
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@ -23,22 +23,39 @@ extern "A" void htif_tick
extern "A" void memory_tick
(
input reg mem_req_valid,
output reg mem_req_ready,
input reg mem_req_store,
input reg [`MEM_ADDR_BITS-1:0] mem_req_bits_addr,
input reg [`MEM_TAG_BITS-1:0] mem_req_bits_tag,
input reg ar_valid,
output reg ar_ready,
input reg [`MEM_ADDR_BITS-1:0] ar_addr,
input reg [`MEM_ID_BITS-1:0] ar_id,
input reg [2:0] ar_size,
input reg [7:0] ar_len,
input reg mem_req_data_valid,
output reg mem_req_data_ready,
input reg [`MEM_DATA_BITS-1:0] mem_req_data_bits,
output reg mem_resp_valid,
input reg mem_resp_ready,
output reg [`MEM_TAG_BITS-1:0] mem_resp_bits_tag,
output reg [`MEM_DATA_BITS-1:0] mem_resp_bits_data
input reg aw_valid,
output reg aw_ready,
input reg [`MEM_ADDR_BITS-1:0] aw_addr,
input reg [`MEM_ID_BITS-1:0] aw_id,
input reg [2:0] aw_size,
input reg [7:0] aw_len,
input reg w_valid,
output reg w_ready,
input reg [`MEM_STRB_BITS-1:0] w_strb,
input reg [`MEM_DATA_BITS-1:0] w_data,
input reg w_last,
output reg r_valid,
input reg r_ready,
output reg [1:0] r_resp,
output reg [`MEM_ID_BITS-1:0] r_id,
output reg [`MEM_DATA_BITS-1:0] r_data,
output reg r_last,
output reg b_valid,
input reg b_ready,
output reg [1:0] b_resp,
output reg [`MEM_ID_BITS-1:0] b_id
);
module rocketTestHarness;
reg [31:0] seed;
@ -47,33 +64,51 @@ module rocketTestHarness;
//-----------------------------------------------
// Instantiate the processor
reg clk = 0;
reg reset = 1;
reg clk = 1'b0;
reg reset = 1'b1;
reg r_reset;
reg start = 0;
reg start = 1'b0;
always #`CLOCK_PERIOD clk = ~clk;
wire mem_req_valid;
reg mem_req_ready;
wire mem_req_bits_rw;
wire [`MEM_ADDR_BITS-1:0] mem_req_bits_addr;
wire [`MEM_TAG_BITS-1:0] mem_req_bits_tag;
wire ar_valid;
reg ar_ready;
wire [`MEM_ADDR_BITS-1:0] ar_addr;
wire [`MEM_ID_BITS-1:0] ar_id;
wire [2:0] ar_size;
wire [7:0] ar_len;
wire mem_req_data_valid;
reg mem_req_data_ready;
wire [`MEM_DATA_BITS-1:0] mem_req_data_bits;
wire aw_valid;
reg aw_ready;
wire [`MEM_ADDR_BITS-1:0] aw_addr;
wire [`MEM_ID_BITS-1:0] aw_id;
wire [2:0] aw_size;
wire [7:0] aw_len;
reg mem_resp_valid;
wire mem_resp_ready;
reg [`MEM_TAG_BITS-1:0] mem_resp_bits_tag;
reg [`MEM_DATA_BITS-1:0] mem_resp_bits_data;
wire w_valid;
reg w_ready;
wire [`MEM_STRB_BITS-1:0] w_strb;
wire [`MEM_DATA_BITS-1:0] w_data;
wire w_last;
reg r_valid;
wire r_ready;
reg [1:0] r_resp;
reg [`MEM_ID_BITS-1:0] r_id;
reg [`MEM_DATA_BITS-1:0] r_data;
reg r_last;
reg b_valid;
wire b_ready;
reg [1:0] b_resp;
reg [`MEM_ID_BITS-1:0] b_id;
reg htif_out_ready;
wire htif_in_valid;
wire [`HTIF_WIDTH-1:0] htif_in_bits;
wire htif_in_ready, htif_out_valid;
wire [`HTIF_WIDTH-1:0] htif_out_bits;
wire htif_out_stats;
wire mem_bk_in_valid;
wire mem_bk_out_valid;
@ -91,25 +126,47 @@ module rocketTestHarness;
wire htif_out_stats_delay; assign #0.1 htif_out_stats = htif_out_stats_delay;
wire mem_req_valid_delay; assign #0.1 mem_req_valid = mem_req_valid_delay;
wire #0.1 mem_req_ready_delay = mem_req_ready;
wire [`MEM_TAG_BITS-1:0] mem_req_bits_tag_delay; assign #0.1 mem_req_bits_tag = mem_req_bits_tag_delay;
wire [`MEM_ADDR_BITS-1:0] mem_req_bits_addr_delay; assign #0.1 mem_req_bits_addr = mem_req_bits_addr_delay;
wire mem_req_bits_rw_delay; assign #0.1 mem_req_bits_rw = mem_req_bits_rw_delay;
wire ar_valid_delay; assign #0.1 ar_valid = ar_valid_delay;
wire #0.1 ar_ready_delay = ar_ready;
wire [`MEM_ADDR_BITS-1:0] ar_addr_delay; assign #0.1 ar_addr = ar_addr_delay;
wire [`MEM_ID_BITS-1:0] ar_id_delay; assign #0.1 ar_id = ar_id_delay;
wire [2:0] ar_size_delay; assign #0.1 ar_size = ar_size_delay;
wire [7:0] ar_len_delay; assign #0.1 ar_len = ar_len_delay;
wire mem_req_data_valid_delay; assign #0.1 mem_req_data_valid = mem_req_data_valid_delay;
wire #0.1 mem_req_data_ready_delay = mem_req_data_ready;
wire [`MEM_DATA_BITS-1:0] mem_req_data_bits_delay; assign #0.1 mem_req_data_bits = mem_req_data_bits_delay;
wire aw_valid_delay; assign #0.1 aw_valid = aw_valid_delay;
wire #0.1 aw_ready_delay = aw_ready;
wire [`MEM_ADDR_BITS-1:0] aw_addr_delay; assign #0.1 aw_addr = aw_addr_delay;
wire [`MEM_ID_BITS-1:0] aw_id_delay; assign #0.1 aw_id = aw_id_delay;
wire [2:0] aw_size_delay; assign #0.1 aw_size = aw_size_delay;
wire [7:0] aw_len_delay; assign #0.1 aw_len = aw_len_delay;
wire #0.1 mem_resp_valid_delay = mem_resp_valid;
wire mem_resp_ready_delay; assign #0.1 mem_resp_ready = mem_resp_ready_delay;
wire [`MEM_TAG_BITS-1:0] #0.1 mem_resp_bits_tag_delay = mem_resp_bits_tag;
wire [`MEM_DATA_BITS-1:0] #0.1 mem_resp_bits_data_delay = mem_resp_bits_data;
wire w_valid_delay; assign #0.1 w_valid = w_valid_delay;
wire #0.1 w_ready_delay = w_ready;
wire [`MEM_STRB_BITS-1:0] w_strb_delay; assign #0.1 w_strb = w_strb_delay;
wire [`MEM_DATA_BITS-1:0] w_data_delay; assign #0.1 w_data = w_data_delay;
wire w_last_delay; assign #0.1 w_last = w_last_delay;
wire #0.1 r_valid_delay = r_valid;
wire r_ready_delay; assign #0.1 r_ready = r_ready_delay;
wire [1:0] #0.1 r_resp_delay = r_resp;
wire [`MEM_ID_BITS-1:0] #0.1 r_id_delay = r_id;
wire [`MEM_DATA_BITS-1:0] #0.1 r_data_delay = r_data;
wire #0.1 r_last_delay = r_last;
wire #0.1 b_valid_delay = b_valid;
wire b_ready_delay; assign #0.1 b_ready = b_ready_delay;
wire [1:0] #0.1 b_resp_delay = b_resp;
wire [`MEM_ID_BITS-1:0] #0.1 b_id_delay = b_id;
wire #0.1 mem_bk_out_ready_delay = mem_bk_out_ready;
wire #0.1 mem_bk_in_valid_delay = mem_bk_in_valid;
wire mem_bk_out_valid_delay; assign #0.1 mem_bk_out_valid = mem_bk_out_valid_delay;
`ifdef FPGA
assign mem_bk_out_valid_delay = 1'b0;
assign htif_out_stats_delay = 1'b0;
`endif
Top dut
(
.clk(clk),
@ -131,26 +188,69 @@ module rocketTestHarness;
.io_mem_backup_ctrl_en(1'b1),
`else
.io_mem_backup_ctrl_en(1'b0),
`endif
`endif // MEM_BACKUP_EN
.io_mem_backup_ctrl_in_valid(mem_bk_in_valid_delay),
.io_mem_backup_ctrl_out_ready(mem_bk_out_ready_delay),
.io_mem_backup_ctrl_out_valid(mem_bk_out_valid_delay),
`endif
`else
.io_host_clk (),
.io_host_clk_edge (),
.io_host_debug_stats_csr (),
.io_mem_req_cmd_valid(mem_req_valid_delay),
.io_mem_req_cmd_ready(mem_req_ready_delay),
.io_mem_req_cmd_bits_rw(mem_req_bits_rw_delay),
.io_mem_req_cmd_bits_addr(mem_req_bits_addr_delay),
.io_mem_req_cmd_bits_tag(mem_req_bits_tag_delay),
.io_mem_backup_ctrl_en (1'b0),
.io_mem_backup_ctrl_in_valid (1'b0),
.io_mem_backup_ctrl_out_ready (1'b0),
.io_mem_backup_ctrl_out_valid (),
`endif // FPGA
.io_mem_req_data_valid(mem_req_data_valid_delay),
.io_mem_req_data_ready(mem_req_data_ready_delay),
.io_mem_req_data_bits_data(mem_req_data_bits_delay),
.io_mem_ar_valid (ar_valid_delay),
.io_mem_ar_ready (ar_ready_delay),
.io_mem_ar_bits_addr (ar_addr_delay),
.io_mem_ar_bits_id (ar_id_delay),
.io_mem_ar_bits_size (ar_size_delay),
.io_mem_ar_bits_len (ar_len_delay),
.io_mem_ar_bits_burst (),
.io_mem_ar_bits_lock (),
.io_mem_ar_bits_cache (),
.io_mem_ar_bits_prot (),
.io_mem_ar_bits_qos (),
.io_mem_ar_bits_region (),
.io_mem_ar_bits_user (),
.io_mem_resp_valid(mem_resp_valid_delay),
.io_mem_resp_ready(mem_resp_ready_delay),
.io_mem_resp_bits_tag(mem_resp_bits_tag_delay),
.io_mem_resp_bits_data(mem_resp_bits_data_delay)
.io_mem_aw_valid (aw_valid_delay),
.io_mem_aw_ready (aw_ready_delay),
.io_mem_aw_bits_addr (aw_addr_delay),
.io_mem_aw_bits_id (aw_id_delay),
.io_mem_aw_bits_size (aw_size_delay),
.io_mem_aw_bits_len (aw_len_delay),
.io_mem_aw_bits_burst (),
.io_mem_aw_bits_lock (),
.io_mem_aw_bits_cache (),
.io_mem_aw_bits_prot (),
.io_mem_aw_bits_qos (),
.io_mem_aw_bits_region (),
.io_mem_aw_bits_user (),
.io_mem_w_valid (w_valid_delay),
.io_mem_w_ready (w_ready_delay),
.io_mem_w_bits_strb (w_strb_delay),
.io_mem_w_bits_data (w_data_delay),
.io_mem_w_bits_last (w_last_delay),
.io_mem_w_bits_user (),
.io_mem_r_valid (r_valid_delay),
.io_mem_r_ready (r_ready_delay),
.io_mem_r_bits_resp (r_resp_delay),
.io_mem_r_bits_id (r_id_delay),
.io_mem_r_bits_data (r_data_delay),
.io_mem_r_bits_last (r_last_delay),
.io_mem_r_bits_user (1'b0),
.io_mem_b_valid (b_valid_delay),
.io_mem_b_ready (b_ready_delay),
.io_mem_b_bits_resp (b_resp_delay),
.io_mem_b_bits_id (b_id_delay),
.io_mem_b_bits_user (1'b0)
);
`ifdef FPGA
@ -165,40 +265,63 @@ module rocketTestHarness;
r_reset <= reset;
if (reset || r_reset)
begin
mem_req_ready <= 0;
mem_req_data_ready <= 0;
mem_resp_valid <= 0;
mem_resp_bits_tag <= 0;
mem_resp_bits_data <= 0;
ar_ready <= 1'b0;
aw_ready <= 1'b0;
w_ready <= 1'b0;
r_valid <= 1'b0;
r_resp <= 2'b0;
r_id <= {`MEM_ID_BITS {1'b0}};
r_data <= {`MEM_DATA_BITS {1'b0}};
r_last <= 1'b0;
b_valid <= 1'b0;
b_resp <= 2'b0;
b_id <= {`MEM_ID_BITS {1'b0}};
end
else
begin
memory_tick
(
mem_req_valid,
mem_req_ready,
mem_req_bits_rw,
mem_req_bits_addr,
mem_req_bits_tag,
ar_valid,
ar_ready,
ar_addr,
ar_id,
ar_size,
ar_len,
mem_req_data_valid,
mem_req_data_ready,
mem_req_data_bits,
mem_resp_valid,
mem_resp_ready,
mem_resp_bits_tag,
mem_resp_bits_data
aw_valid,
aw_ready,
aw_addr,
aw_id,
aw_size,
aw_len,
w_valid,
w_ready,
w_strb,
w_data,
w_last,
r_valid,
r_ready,
r_resp,
r_id,
r_data,
r_last,
b_valid,
b_ready,
b_resp,
b_id
);
end
end
wire mem_bk_req_valid, mem_bk_req_rw, mem_bk_req_data_valid;
wire [`MEM_TAG_BITS-1:0] mem_bk_req_tag;
wire [`MEM_ID_BITS-1:0] mem_bk_req_tag;
wire [`MEM_ADDR_BITS-1:0] mem_bk_req_addr;
wire [`MEM_DATA_BITS-1:0] mem_bk_req_data_bits;
wire mem_bk_req_ready, mem_bk_req_data_ready, mem_bk_resp_valid;
wire [`MEM_TAG_BITS-1:0] mem_bk_resp_tag;
wire [`MEM_ID_BITS-1:0] mem_bk_resp_tag;
wire [`MEM_DATA_BITS-1:0] mem_bk_resp_data;
`ifdef MEM_BACKUP_EN
@ -251,15 +374,16 @@ module rocketTestHarness;
);
`else
// set dessert outputs to zero when !backupmem_en
assign mem_bk_out_ready = 0;
assign mem_bk_in_valid = 0;
assign mem_in_bits = 0;
assign mem_bk_req_valid = 0;
assign mem_bk_req_addr = 0;
assign mem_bk_req_rw = 0;
assign mem_bk_req_tag = 0;
assign mem_bk_req_data_valid = 0;
assign mem_bk_req_data_bits = 0;
assign mem_bk_out_ready = 1'b0;
assign mem_bk_in_valid = 1'b0;
assign mem_in_bits = {`HTIF_WIDTH {1'b0}};
assign mem_bk_req_valid = 1'b0;
assign mem_bk_req_ready = 1'b0;
assign mem_bk_req_addr = {`MEM_ADDR_BITS {1'b0}};
assign mem_bk_req_rw = 1'b0;
assign mem_bk_req_tag = {`MEM_ID_BITS {1'b0}};
assign mem_bk_req_data_valid = 1'b0;
assign mem_bk_req_data_bits = 16'd0;
`endif
reg htif_in_valid_premux;
@ -392,13 +516,13 @@ module rocketTestHarness;
begin
$fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
`VCDPLUSCLOSE
htif_fini(1);
htif_fini(1'b1);
end
if (exit == 1)
begin
`VCDPLUSCLOSE
htif_fini(0);
htif_fini(1'b0);
end
end
@ -430,9 +554,24 @@ module rocketTestHarness;
always @(posedge clk)
begin
if (verbose && mem_req_valid && mem_req_ready)
if (verbose)
begin
$fdisplay(stderr, "MC: rw=%d addr=%x", mem_req_bits_rw, {mem_req_bits_addr,6'd0});
if (ar_valid && ar_ready)
begin
$fdisplay(stderr, "MC: ar addr=%x", ar_addr);
end
if (aw_valid && aw_ready)
begin
$fdisplay(stderr, "MC: aw addr=%x", aw_addr);
end
if (w_valid && w_ready)
begin
$fdisplay(stderr, "MC: w data=%x", w_data);
end
if (r_valid && r_ready)
begin
$fdisplay(stderr, "MC: r data=%x", r_data);
end
end
end