riscv/rocket-chip
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Remove HTIF; use debug module for testing in simulation

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This commit is contained in:
Andrew Waterman
2016-06-23 00:17:29 -07:00
parent 255ef05e21
commit 30331fcaeb
12 changed files with 198 additions and 387 deletions
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56
vsrc/rocketTestHarness.v
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@ -1,18 +1,21 @@
// See LICENSE for license details.
extern "A" void htif_fini(input reg failure);
extern "A" void do_exit(input reg failure);
extern "A" void htif_tick
extern "A" void debug_tick
(
output reg htif_in_valid,
input reg htif_in_ready,
output reg [`HTIF_WIDTH-1:0] htif_in_bits,
output reg debug_req_valid,
input reg debug_req_ready,
output reg [ 4:0] debug_req_bits_addr,
output reg [ 1:0] debug_req_bits_op,
output reg [33:0] debug_req_bits_data,
input reg htif_out_valid,
output reg htif_out_ready,
input reg [`HTIF_WIDTH-1:0] htif_out_bits,
input reg debug_resp_valid,
output reg debug_resp_ready,
input reg [ 1:0] debug_resp_bits_resp,
input reg [33:0] debug_resp_bits_data,
output reg [31:0] exit
output reg [31:0] exit
);
extern "A" void memory_tick
@ -68,7 +71,6 @@ module rocketTestHarness;
always #`CLOCK_PERIOD clk = ~clk;
reg [ 31:0] n_mem_channel = `N_MEM_CHANNELS;
reg [ 31:0] htif_width = `HTIF_WIDTH;
reg [ 31:0] mem_width = `MEM_DATA_BITS;
reg [ 63:0] max_cycles = 0;
reg [ 63:0] trace_count = 0;
@ -79,12 +81,6 @@ module rocketTestHarness;
wire printf_cond = verbose && !reset;
integer stderr = 32'h80000002;
reg htif_out_ready;
reg htif_in_valid;
reg [`HTIF_WIDTH-1:0] htif_in_bits;
wire htif_in_ready, htif_out_valid;
wire [`HTIF_WIDTH-1:0] htif_out_bits;
`include `TBVFRAG
always @(posedge clk)
@ -94,24 +90,26 @@ module rocketTestHarness;
reg [31:0] exit = 0;
always @(posedge htif_clk)
always @(posedge clk)
begin
if (reset || r_reset)
begin
htif_in_valid <= 0;
htif_out_ready <= 0;
exit <= 0;
debug_req_valid <= 0;
debug_resp_ready <= 0;
end
else
begin
htif_tick
debug_tick
(
htif_in_valid,
htif_in_ready,
htif_in_bits,
htif_out_valid,
htif_out_ready,
htif_out_bits,
debug_req_valid,
debug_req_ready,
debug_req_bits_addr,
debug_req_bits_op,
debug_req_bits_data,
debug_resp_valid,
debug_resp_ready,
debug_resp_bits_resp,
debug_resp_bits_data,
exit
);
end
@ -161,7 +159,7 @@ module rocketTestHarness;
begin
$fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
`VCDPLUSCLOSE
htif_fini(1'b1);
do_exit(1'b1);
end
if (exit == 1)
@ -169,7 +167,7 @@ module rocketTestHarness;
if (verbose)
$fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
`VCDPLUSCLOSE
htif_fini(1'b0);
do_exit(1'b0);
end
end