riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
3,059 Commits 1 Branch 0 Tags 13 MiB
96e2cefb34
Commit Graph

3059 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Wesley W. Terpstra
46fc9744e2 rocket: add an AXI master port into the chip 2016-07-11 12:16:44 -07:00
Wesley W. Terpstra
8ac7fa5544 ext: support multiple external AHB/AXI ports 2016-07-11 12:16:39 -07:00
Howard Mao
e194677087 fix comparator PutBlock data generation and debug output 2016-07-11 12:15:37 -07:00
mwachs5
36720d915a Update README.md (#161) 
Correct typo in heading
 2016-07-11 00:34:13 -07:00
Andrew Waterman
9751ea0f35 Fix Verilator VCD (#157) 2016-07-09 02:37:39 -07:00
Andrew Waterman
1699622730 Don't speculatively refill I$ in uncacheable regions 2016-07-09 01:10:58 -07:00
Howard Mao
5a3d6a1583 NastiTest should cycle through write ids 2016-07-08 17:55:02 -07:00
Howard Mao
9ec55ebb91 don't add io:ext region to address map if no external MMIO 2016-07-08 15:29:35 -07:00
Howard Mao
35547aa428 allow NastiConverterTest and Memtest to run simultaneously 2016-07-08 13:40:52 -07:00
Howard Mao
d80c2f480f make NastiConverterTest act as generator and share blocks 2016-07-08 13:39:46 -07:00
Howard Mao
358668699f refactoring groundtest configuration 2016-07-08 11:40:16 -07:00
Howard Mao
850fa092a4 refactor how groundtests are configured 2016-07-08 11:40:01 -07:00
Howard Mao
eeac405ef8 get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache 2016-07-08 09:33:07 -07:00
Howard Mao
8aa73915a1 put locking arbiter back into converter 2016-07-08 09:31:33 -07:00
Howard Mao
a50ba39ea7 Revert "add buffering and locking to TL -> Nasti converter" 
This reverts commit 2109a48e18719383942d535ff4c1d0a859dcc424.

Conflicts:
	src/main/scala/converters/Nasti.scala
 2016-07-08 09:31:33 -07:00
Andrew Waterman
32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Andrew Waterman
70b677ecda Vec considered harmful; use isOneOf instead (#64) 
Vec is heavyweight and really should only be used for I/O and
dynamic indexing.  A recurring pattern in uncore is

    Vec(const1, const2, const3) contains x

which is nice but has a deleterious effect on simulation copilation
and execution time.  This patch proposes an alternative:

    x isOneOf (const1, const2, const3)
    x isOneOf seqOfThings

I think it's also more idiomatic.

This is just a prototype; I'm not wed to the name or implementation.
 2016-07-07 19:25:57 -07:00
Howard Mao
f7b392306e make sure SimpleHellaCacheIF can work with blocking DCache 2016-07-07 18:59:23 -07:00
Howard Mao
f62c74b82a allow groundtest to use non-blocking DCache 2016-07-07 18:59:09 -07:00
Andrew Waterman
3d8939d3c3 Set misa.base = 1 for RV32 2016-07-07 15:32:21 -07:00
Andrew Waterman
2455a806af Make WFI instruction respect mie CSR setting 2016-07-07 15:31:17 -07:00
Howard Mao
67871654dd start NastiConverterTest higher up in memory 2016-07-07 14:35:04 -07:00
Howard Mao
16a6b11081 fix bug in AXI -> TL converter 2016-07-07 14:34:24 -07:00
Howard Mao
7cc64011fb simplify amo_mask generation 2016-07-07 12:14:45 -07:00
Howard Mao
1c5e7be75b make sure Nasti write channel id is set correctly 2016-07-07 12:14:02 -07:00
Howard Mao
6055482513 make sure write channel id is actually set 2016-07-07 12:12:39 -07:00
Howard Mao
8ccc50a8f0 fix IdMapper and TL -> NASTI converter 2016-07-07 10:16:44 -07:00
Howard Mao
8c13e78ab5 add buffering and locking to TL -> AXI converter 2016-07-06 16:57:09 -07:00
Howard Mao
e27cb5f885 fix voluntary release issue in L2 cache 2016-07-06 16:57:01 -07:00
Howard Mao
9f7845f043 don't test BRAMSlave for now 2016-07-06 16:56:14 -07:00
Howard Mao
5d8d5e598b add buffering and locking to TL -> Nasti converter 2016-07-06 16:51:45 -07:00
Andrew Waterman
35a983275e Guarantee one-hotness of BTB entries 2016-07-06 15:58:01 -07:00
Howard Mao
bbf780725f add NastiReadIO and NastiWriteIO bundles 2016-07-06 15:13:04 -07:00
Howard Mao
b10d306b4a add option to log L2 cache transactions for easier debugging 2016-07-06 14:59:09 -07:00
Howard Mao
64afc795fd make sure voluntary releases don't get allocated to L2WritebackUnit 2016-07-06 14:10:45 -07:00
Andrew Waterman
2a146155fc Update to new priv-1.9 PTE format 2016-07-06 10:15:59 -07:00
Andrew Waterman
8625f9ea0c Update PTE format 2016-07-06 03:20:41 -07:00
Andrew Waterman
c0e6ecebfc Fix BTB perf bug 
In rare cases, it would replace into a different row than it recorded.
 2016-07-06 03:16:05 -07:00
Andrew Waterman
f3e22984d5 Remove uarch counters 
These will be replaced with the indirect TDR scheme used by breakpoints.
 2016-07-06 01:41:41 -07:00
Andrew Waterman
25fdabdd59 Don't implicitly create Vecs, since they're heavyweight 2016-07-06 01:41:31 -07:00
Andrew Waterman
8bd7e3932b Implement priv-1.9 PTE scheme 2016-07-05 19:19:49 -07:00
Howard Mao
f79a3285fb fix TraceGen and Nasti -> TL converter 2016-07-05 17:42:57 -07:00
Howard Mao
b105076996 fix ID mapper to disallow two in-flight requests with the same inner ID 2016-07-05 17:41:46 -07:00
Howard Mao
af76837970 conform to new NastiWriteDataChannel interface 2016-07-05 17:41:46 -07:00
Howard Mao
ee624b1c6e make NastiSmallTest a bit more intensive 2016-07-05 17:31:51 -07:00
Howard Mao
96f09003f2 use options for NastiWriteDataChannel write mask 2016-07-05 16:03:25 -07:00
Albert Ou
4c07aedfad Rewrite BRAMSlave to infer a single BRAM instance 2016-07-05 14:21:21 -07:00
Howard Mao
8c5fd86f9b fix tracegen module and scripts 2016-07-05 13:50:17 -07:00
Howard Mao
c924ec2a22 fixing bufferless broadcast hub 2016-07-05 12:10:22 -07:00
Howard Mao
702444709a make sure pending bits updated for all releases 2016-07-05 12:08:22 -07:00