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fix tracegen module and scripts

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This commit is contained in:
Howard Mao 2016-07-05 13:50:17 -07:00
parent 61a44dcfc3
commit 8c5fd86f9b
4 changed files with 13 additions and 20 deletions
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9
groundtest/scripts/tracegen+check.sh
View File

@ -37,7 +37,6 @@ AXE=${AXE-axe}
MODEL=${MODEL-WMO}
LOG_DIR=${LOG_DIR-tracegen-log}
TRACE_STATS=${TRACE_STATS-tracestats.py}
ELF_FILE=${ELF_FILE-../riscv-tools/riscv-tests/build/isa/rv64ui-p-simple}
###############################################################################
@ -76,12 +75,6 @@ if [ ! `command -v $TRACE_STATS` ]; then
exit -1
fi
if [ ! -f $ELF_FILE ]; then
echo Can\'t find dummy elf file for ground tests
echo Please run build.sh in riscv-tools to produce \'rv64ui-p-simple\'
exit -1
fi
if [ "$MODEL" != SC -a \
"$MODEL" != TSO -a \
"$MODEL" != PSO -a \
@ -119,7 +112,7 @@ for (( I = $START_SEED; I <= $END_SEED; I++ )); do
fi
# Generate trace
$TRACE_GEN $EMU $I $ELF_FILE > $LOG/trace.txt
$TRACE_GEN $EMU $I > $LOG/trace.txt
if [ ! $? -eq 0 ]; then
echo -e "\n\nError: emulator returned non-zero exit code"
echo See $LOG/trace.txt for details

6
groundtest/scripts/tracegen.py
View File

@ -33,12 +33,12 @@ import subprocess
import re
def main():
if len(sys.argv) != 4:
sys.stderr.write("Usage: tracegen.py EMULATOR SEED ELF\n")
if len(sys.argv) != 3:
sys.stderr.write("Usage: tracegen.py EMULATOR SEED\n")
sys.exit(-1)
p = subprocess.Popen([sys.argv[1],
"+verbose", "-s" + sys.argv[2], sys.argv[3]],
"+verbose", "-s" + sys.argv[2]],
stderr=subprocess.PIPE, stdout=subprocess.PIPE)
if p == None:
sys.stderr.write("File not found: " + sys.argv[1] + "\n")

2
groundtest/src/main/scala/tracegen.scala
View File

@ -62,7 +62,7 @@ trait HasTraceGenParams {
val numGens = p(NTiles)
val numBitsInId = log2Up(numGens)
val numReqsPerGen = p(MaxGenerateRequests)
val memRespTimeout = 1024
val memRespTimeout = 8192
val numBitsInWord = p(WordBits)
val numBytesInWord = numBitsInWord / 8
val numBitsInWordOffset = log2Up(numBytesInWord)

16
groundtest/src/main/scala/util.scala
View File

@ -53,15 +53,15 @@ object Timer {
// Timer with a dynamically-settable period.
class DynamicTimer(width: Int) extends Module {
class DynamicTimer(w: Int) extends Module {
val io = new Bundle {
val start = Bool(INPUT)
val period = UInt(INPUT, width)
val period = UInt(INPUT, w)
val stop = Bool(INPUT)
val timeout = Bool(OUTPUT)
}
val countdown = Reg(init = UInt(0, width))
val countdown = Reg(init = UInt(0, w))
val active = Reg(init = Bool(false))
when (io.start) {
@ -104,14 +104,14 @@ class LCG16 extends Module {
// An n-bit psuedo-random generator made from many instances of a
// 16-bit LCG. Parameter 'width' must be larger than 0.
class LCG(val width : Int) extends Module {
class LCG(val w : Int) extends Module {
val io = new Bundle {
val out = UInt(OUTPUT, width)
val out = UInt(OUTPUT, w)
}
require(width > 0)
val numLCG16s : Int = (width+15)/16
require(w > 0)
val numLCG16s : Int = (w+15)/16
val outs = List.fill(numLCG16s)(Module(new LCG16()).io.out)
io.out := Cat( outs(0)((width%16)-1, 0)
io.out := Cat( outs(0)((w%16)-1, 0)
, outs.drop(1) : _*)
}