1
0
Commit Graph

97 Commits

Author SHA1 Message Date
Colin Schmidt
8516e38eb2 remove implicit modulo addressing in FPU (#44) 2016-06-09 11:33:33 -07:00
Christopher Celio
2d6f35525e Added Field[Int] to SFMALatency/DFMALatency params 2016-04-06 14:50:57 -07:00
Andrew Waterman
7ae44d4905 Add RV32 support 2016-03-10 17:32:00 -08:00
Christopher Celio
31dd311aff [fpu] fix rounding mode bug in fdivfsqrt 2016-02-08 17:38:31 -08:00
Howard Mao
120361226d fix more Chisel3 deprecations 2016-01-14 14:46:31 -08:00
Andrew Waterman
ae98af7077 don't mix SInt/UInt 2016-01-12 16:27:36 -08:00
Andrew Waterman
7bf503a275 Remove four integer/FP converters 2016-01-12 16:06:23 -08:00
Howard Mao
13ce91e453 fix Chisel3 compat warnings in ICache and FPU 2016-01-12 12:43:48 -08:00
Yunsup Lee
5e2698adbc Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-14 16:44:55 -08:00
Yunsup Lee
213c1a4c81 fix fdiv/fsqrt control bug in fpu 2015-11-14 16:43:15 -08:00
Yunsup Lee
4dd097d156 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-14 14:52:13 -08:00
Yunsup Lee
3c3c946755 move to new version of hardfloat 2015-11-14 14:49:17 -08:00
Yunsup Lee
df5daaa72e Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-06 23:57:42 -08:00
Andrew Waterman
2f515b2af6 Reduce critical path for fdiv valid signal 2015-11-06 23:28:31 -08:00
Colin Schmidt
652fb393a3 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-10-22 16:38:28 -07:00
Henry Cook
4f8468b60f depend on external cde library 2015-10-21 18:19:23 -07:00
Colin Schmidt
2cee8c8bec Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port 2015-10-18 13:09:17 -07:00
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Andrew Waterman
833909a2b5 Chisel3 compatibility fixes 2015-09-30 14:36:26 -07:00
Andrew Waterman
e72e5a34b5 Fix storage of SP values in DP registers
The SFMA was zero-extending the SP value to 65 bits, rather than filling
the upper 32 bits with 1s.  This meant that an FSD + FLD of that register
would not restore the value properly.

Also, minor code cleanup.
2015-09-21 12:20:44 -07:00
Christopher Celio
76bf1da310 [commitlog] zero-extend SP write-back values 2015-09-15 16:47:26 -07:00
Christopher Celio
7d14abf262 [commitlog] Added privilege-level to output 2015-09-15 16:47:24 -07:00
Christopher Celio
53a02a62c8 [commitlog] Fix sp/dp bug in FPU writeback 2015-09-15 16:46:47 -07:00
Christopher Celio
d630a03857 [commitlog] Added FP instructions to the commitlog 2015-09-15 15:59:13 -07:00
Andrew Waterman
78b2e947de Chisel3 compatibility fixes 2015-09-11 15:43:07 -07:00
Colin Schmidt
cab12635f8 Merge master into rocc-fpu-port
ebb33f2f4b658211960a4c6c023c139420c67212
2015-08-06 08:03:10 -07:00
Andrew Waterman
1718333f83 Don't use Vec as lvalue 2015-08-05 15:29:33 -07:00
Andrew Waterman
546205b174 Chisel3 compatibility: use >>Int instead of >>UInt 2015-08-05 15:29:03 -07:00
Andrew Waterman
6c0e1e33ab Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00
Andrew Waterman
57930e8a26 Chisel3 compatibility potpourri 2015-07-30 23:53:02 -07:00
Andrew Waterman
049fc8dc24 Chisel3 compatibility: use BitPat for don't-cares
This one's hella ugly, but for the time being, idgaf.
2015-07-28 02:48:49 -07:00
Andrew Waterman
ae73e3a997 Only instantiate div/sqrt unit if requested 2015-07-22 22:18:18 -07:00
Andrew Waterman
cc447c8110 Refactor pipeline RTL (merge ctrl + dpath into rocket) 2015-07-21 17:10:56 -07:00
Andrew Waterman
ac6e73e317 Add Wire() wrap 2015-07-15 20:24:18 -07:00
Andrew Waterman
be2ff6dec7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:33:46 -07:00
Colin Schmidt
c746ef8702 fix bug in rocc port resp for FPtoInt instructions 2015-05-04 11:20:55 -07:00
Colin Schmidt
bd72db92c1 update rocc port to use fdiv/sqrt 2015-04-07 15:02:02 -07:00
Colin Schmidt
887a8de189 Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port 2015-04-06 13:48:44 -07:00
Andrew Waterman
9ade0e41cc Integrate divide/sqrt unit 2015-04-04 16:39:17 -07:00
Colin Schmidt
a369d8f17f Add fpu port to the rocc interface 2015-04-02 01:30:11 -07:00
Yunsup Lee
8abf62fae3 add LICENSE 2014-09-12 18:06:41 -07:00
Adam Izraelevitz
812353bace Ported FPU parameters to new Chisel Parameters 2014-08-19 11:37:27 -07:00
Andrew Waterman
4ca152b012 Use BundleWithConf to avoid clone method boilerplate 2014-05-09 19:37:16 -07:00
Andrew Waterman
5996418021 Fix exception behavior of fmin/fmax 2014-03-18 18:36:51 -07:00
Andrew Waterman
a0389645b7 New FP encoding; improved FP implementation 2014-03-11 18:58:24 -07:00
Andrew Waterman
00bc1a2293 Add fclass.{s|d} instructions 2014-03-10 16:59:24 -07:00
Andrew Waterman
c7110c8389 Make FPU pipeline depths configurable 2014-02-28 13:39:59 -08:00
Andrew Waterman
95de358a96 More of the same FPU fix
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
2014-01-17 14:09:30 -08:00
Andrew Waterman
cf38001e98 Fix fmv.s.x -> fsd 2014-01-17 03:52:35 -08:00
Andrew Waterman
924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00