This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control. But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
- Global history only contains branches.
- Only update BHT and history on BTB hits.
- Gate off speculative update on stall or icmiss.
- Fixed bug where BHT updates were delayed a cycle.
- No longer update global history in fetch stage.
- Only update global history when instruction is a branch.
- Does allow for the possibility of back-to-back branches to see
slightly different histories on subsequent executions.
- Updated in fetch speculatively.
* Updates gated off by cpu.resp.fire().
* BTB direction factored into history update.
- All branches update the BHT.
- Each instruction carries history; index into BHT is recomputed by
passing in mem_reg_pc.
- The nbdache (among others?) use CoreParameters, which has nothing to do with RetireWidth requirements.
- This conflicts with other cores which uses nbdcache.
- RocketCoreParameters may be unneccessary, and the require() check can be moved deeper into Rocket.
It was possible to take an interrupt on the instruction in the shadow of
a short forward branch. EPC would thus get the wrong value, and so
a wrong-path instruction would be executed upon return from interrupt.
h/t Yunsup
