6ee6ea4f1e
use Put/Get/PutBlock/GetBlock constructors in broadcast hub
2015-09-14 12:57:54 -07:00
ae3d96013a
make TL -> NASTI converter ingest ClientUncachedTileLinkIO and move functionality to Unwrapper
2015-09-14 12:57:54 -07:00
21f96f382c
split off SCR functionality from HTIF
2015-09-14 12:57:54 -07:00
bdc6972a8d
separate RTC updates from HTIF
2015-09-14 12:56:44 -07:00
24f3fac90a
fix broadcast hub and TL -> NASTI converter to support subblock operations
2015-09-14 12:56:44 -07:00
24389a5257
Chisel3 compatibility fixes
2015-09-11 15:41:39 -07:00
350d530766
Use Vec.fill, not Vec.apply, for Vec literals
2015-08-27 10:00:43 -07:00
94287fed90
Avoid type-unsafe assignments
2015-08-27 09:57:36 -07:00
05d311c517
Use Vec.apply, not Vec.fill, for type nodes
2015-08-27 09:47:02 -07:00
005752e2a6
use the parameters used to create the original object
2015-08-10 14:43:17 -07:00
01fc61ba96
Don't construct so many Vecs
2015-08-05 18:43:59 -07:00
a551a12d70
add missing Wire wrap in BasicCrossbar
2015-08-05 17:05:31 -07:00
eb6583d607
use cloneType in PhysicalNetworkIO
2015-08-05 16:47:49 -07:00
798ddeb5f5
Chisel3 compatibility: use >>Int instead of >>UInt
...
The latter doesn't contract widths anymore.
2015-08-04 13:15:17 -07:00
fb718f03c1
bump scala to 2.11.6
2015-08-03 19:50:58 -07:00
77cf26aeba
Chisel3: Flip order of := and <>
2015-08-03 18:53:39 -07:00
121e4fb511
Flip direction of some bulk connects
2015-08-03 18:01:14 -07:00
a21979a2fa
Bits -> UInt
2015-08-03 18:01:06 -07:00
9c7a41e8d3
Chisel3: bulk connect is not commutative
...
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:09:00 -07:00
6fc807f069
Chisel3: Avoid subword assignment
2015-08-01 21:08:35 -07:00
6d574f8c1b
Fix incompatible assignment
2015-07-31 00:59:34 -07:00
377e17e811
Add Wire() wrap
2015-07-31 00:32:02 -07:00
0686bdbe28
Avoid cross-module references
...
You can't instantiate a Vec in one module and use it in another.
An idiosyncrasy of the Chisel2 implementation let this one slip by.
In this case, it's just a matter of using def instead of val.
2015-07-30 23:49:06 -07:00
8f7b390353
UInt-> Bits; avoid mixed UInt/SInt code
2015-07-30 23:49:06 -07:00
6c391e3b37
Use UInt(0), not UInt(width=0), for constant 0
2015-07-30 23:49:06 -07:00
4c0f996808
Fix typo (juntion -> junctions).
2015-07-30 14:50:28 -07:00
c70b495f6d
moved buses to junctions repo
2015-07-29 18:04:30 -07:00
8b1ab23347
update README.md
2015-07-29 11:49:21 -07:00
4daa20b5fe
simplify .sbt files
2015-07-29 11:49:20 -07:00
a69c749249
Fix compilation with scala 2.11.6
...
We forgot to specify return types on overloaded methods, and a previous
version of the scala compiler failed to flag this as an error.
2015-07-28 16:24:45 -07:00
f8ec6d6393
Chisel3 compatibility: use BitPat for don't-cares
...
Also, call the UInt factory instead of the Bits one, for good measure.
2015-07-28 02:46:23 -07:00
0e06c941df
Chisel3 compatibility fixes
2015-07-23 14:58:46 -07:00
3c0475e08b
Add Wire() wrap
2015-07-15 20:24:03 -07:00
2d6b3b2331
Don't use clone
2015-07-15 18:06:27 -07:00
276f53b652
Delete BigMem; it's not used anymore
2015-07-15 17:41:47 -07:00
15cec0eab7
Vec(Reg) -> Reg(Vec)
2015-07-15 12:44:54 -07:00
e76a9d3493
Chisel3: Don't mix Mux types
2015-07-11 14:05:39 -07:00
5dc3da008e
Use Chisel3 SeqMem construct
2015-07-11 13:36:26 -07:00
fb91e3e1ab
minor metadata API update (0.3.3)
2015-07-09 14:36:09 -07:00
80ad1eac70
Update README.md
2015-07-08 19:05:18 -07:00
55059632c4
Temporarily use HTIF to push RTC value to cores
2015-07-05 16:19:39 -07:00
d7cb60e8fa
L2 WritebackUnit bug fix
2015-07-02 13:52:40 -07:00
b4e38192a1
Fix (?) L2$ miss bug
...
The victim's metadata was incorrectly used for the new line.
2015-06-24 18:01:56 -07:00
ea76800d1a
Fix data array reset bug
...
io.resp.valid could have been valid the cycle after reset, causing the
write mask in the acquire tracker to have an erroneous value after reset.
This caused the L1 I$ to be refilled with the wrong data.
This probably only affects programs loaded with +loadmem and so shouldn't
matter for the EOS24 silicon. It should only affect the first L2 xact,
which, in practice, would be an HTIF write to load the program.
2015-06-11 15:28:23 -07:00
f3a838cedf
nasti converters, hub bugfix
2015-05-21 19:49:17 -07:00
c202449e34
first version NASTI IOs
2015-05-14 15:29:49 -07:00
90c9ee7b04
fix unalloc putblocks
2015-05-14 12:37:35 -07:00
a7fa77c7fc
track operand size for Gets
2015-05-13 23:28:18 -07:00
172c372d3e
L2 alloc cleanup
2015-05-12 17:14:06 -07:00
5fdae2cb61
Merge branch 'master' of github.com:ucb-bar/uncore
2015-05-07 16:18:23 -07:00
