Howard Mao
|
3b0e9167fa
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add AXI to AHB converter and more conformant HASTI RAM
|
2016-05-06 11:32:03 -07:00 |
|
Howard Mao
|
3e759d2575
|
add Hasti test to unit test
|
2016-05-06 11:31:43 -07:00 |
|
Howard Mao
|
1ed6d6646d
|
move NastiROM and HastiRAM into rom.scala and bram.scala
|
2016-05-06 11:31:22 -07:00 |
|
Howard Mao
|
77e859760c
|
add a Hasti RAM alongside the Nasti ROM
|
2016-05-06 11:31:22 -07:00 |
|
Howard Mao
|
44740cb6b2
|
parameterize Hasti address and data bits
|
2016-05-06 11:30:50 -07:00 |
|
Howard Mao
|
64991d3947
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add AXI to AHB converter
|
2016-05-06 11:30:50 -07:00 |
|
Howard Mao
|
a875eb9c31
|
update riscv-tools for bbl fix
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2016-05-05 19:36:34 -07:00 |
|
Colin Schmidt
|
8fa2de0816
|
chisel3 fix to RoCC connections honor last connect
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2016-05-05 18:09:48 -07:00 |
|
Howard Mao
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18ffe7b1ec
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don't use +verbose in vsim .run rule
|
2016-05-04 23:01:14 -07:00 |
|
Andrew Waterman
|
8b06947446
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Run bmarks faster (hopefully)
|
2016-05-04 22:47:34 -07:00 |
|
Howard Mao
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f1baa4aecc
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update riscv-tests so that mm benchmark doesn't run forever
|
2016-05-04 21:28:55 -07:00 |
|
Howard Mao
|
dfcb73b6c9
|
groundtest only needs to write to a single tohost
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2016-05-03 20:21:13 -07:00 |
|
Howard Mao
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1882e694e4
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only write to a single tohost location
|
2016-05-03 20:20:52 -07:00 |
|
Howard Mao
|
4045a07eda
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Remove need for separate riscv-tests for groundtest
|
2016-05-03 18:29:46 -07:00 |
|
Howard Mao
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8f891437b5
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fix CacheFillTest
|
2016-05-03 14:57:05 -07:00 |
|
Andrew Waterman
|
15f4af19cf
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Remove HTIF CPU port
|
2016-05-03 13:55:59 -07:00 |
|
Andrew Waterman
|
9dd23a603a
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Remove HTIF port
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2016-05-03 13:41:58 -07:00 |
|
Howard Mao
|
6cb0979ac4
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fix CacheFillTest
|
2016-05-03 13:35:38 -07:00 |
|
Howard Mao
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487d0b356e
|
fixes to get groundtest working with priv-1.9 changes
|
2016-05-03 13:09:44 -07:00 |
|
Howard Mao
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518d510622
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only write out finish from tile 0 in groundtest
|
2016-05-03 13:09:22 -07:00 |
|
Howard Mao
|
f26c422544
|
assert that TileLink router has valid route
|
2016-05-03 12:18:06 -07:00 |
|
Howard Mao
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b95f095aca
|
write to multiple possible tohost locations
|
2016-05-02 20:11:20 -07:00 |
|
Andrew Waterman
|
5352497edb
|
MPRV takes effect regardless of privilege mode
|
2016-05-02 19:53:25 -07:00 |
|
Howard Mao
|
4b4e8f7f62
|
fixes for priv-1.9 changes
|
2016-05-02 18:25:02 -07:00 |
|
Howard Mao
|
5cbcc41515
|
get rid of unused imports
|
2016-05-02 18:23:46 -07:00 |
|
Howard Mao
|
be21f6962b
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make GlobalAddrHashMap a config variable
|
2016-05-02 18:22:43 -07:00 |
|
Andrew Waterman
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c7c8ae5468
|
Instantiate PRCI block
|
2016-05-02 18:08:33 -07:00 |
|
Andrew Waterman
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f784f4da93
|
Rename PRCICoreIO to PRCITileIO
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2016-05-02 18:08:01 -07:00 |
|
Andrew Waterman
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cc4102f8de
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Add trivial version of PRCI block
It doesn't really do anything besides deliver deliver IPIs yet.
|
2016-05-02 17:49:10 -07:00 |
|
Andrew Waterman
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6d1e82bddf
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Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port
|
2016-05-02 15:21:55 -07:00 |
|
Andrew Waterman
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72731de25a
|
Take a stab at the PRCI-Rocket interface
|
2016-05-02 15:20:33 -07:00 |
|
Andrew Waterman
|
000e20f937
|
Remove MIPI; make mip.MSIP read-only
The PRCI block outside the core will provide IPIs eventually
|
2016-05-02 15:18:41 -07:00 |
|
Andrew Waterman
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83fa489cef
|
Stop using HTIF CSR port
The port itself is still present to keep other stuff compiling.
|
2016-05-02 14:40:52 -07:00 |
|
Andrew Waterman
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c4d2d29e80
|
Stub out debug module, rather than leaving it floating
|
2016-04-30 22:37:39 -07:00 |
|
Albert Ou
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0ff4fd0ccd
|
Fix IOMSHR to send finishes for stores
|
2016-04-30 22:20:29 -07:00 |
|
Andrew Waterman
|
46bbbba5e6
|
New address map
|
2016-04-30 20:59:36 -07:00 |
|
Andrew Waterman
|
695c4c5096
|
Support both Get and GetBlock on ROMSlave
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2016-04-30 17:34:12 -07:00 |
|
Andrew Waterman
|
491184a8f8
|
ERET -> xRET; remove mcfgaddr
|
2016-04-30 17:32:51 -07:00 |
|
Andrew Waterman
|
5af98145b9
|
don't signal bad physical address on TLB miss
|
2016-04-30 17:31:46 -07:00 |
|
Albert Ou
|
6f052a740c
|
Add TileLink BRAM slave
|
2016-04-29 14:10:44 -07:00 |
|
Andrew Waterman
|
d0aa4c722d
|
More WIP on new memory map
|
2016-04-28 16:15:31 -07:00 |
|
Andrew Waterman
|
cae4265f3b
|
Change mcfgaddr pointer
|
2016-04-28 16:14:05 -07:00 |
|
Andrew Waterman
|
e4ace55d77
|
Address Map refactoring
|
2016-04-28 16:12:35 -07:00 |
|
Andrew Waterman
|
1df68a25fd
|
Address Map refactoring
|
2016-04-28 16:08:58 -07:00 |
|
Wei Song
|
ed5bdf3c23
|
print the base address of each SCR as indicated
|
2016-04-28 16:31:56 +01:00 |
|
Andrew Waterman
|
1f211b37df
|
WIP on new memory map
|
2016-04-27 14:57:54 -07:00 |
|
Andrew Waterman
|
739cf07637
|
Remove mtime/mtimecmp
The RTC is now a device that lives on the MMIO bus.
|
2016-04-27 14:54:51 -07:00 |
|
Andrew Waterman
|
81ff127dc3
|
Clean up TileLinkRecursiveInterconnect a bit
|
2016-04-27 14:53:11 -07:00 |
|
Andrew Waterman
|
c8b1f0801b
|
Remove start address option from AddrMapEntries
It appears to never be used, and clutters things. The new invariant is
that AddrMaps are relative and AddrHashMaps are absolute.
|
2016-04-27 14:52:05 -07:00 |
|
Andrew Waterman
|
d3dee2c6c6
|
support countSlaves on empty address maps
|
2016-04-27 14:51:52 -07:00 |
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