Andrew Waterman
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3479f1c6cd
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add LR/SC support
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2013-04-07 19:25:20 -07:00 |
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Andrew Waterman
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e74e032c87
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simplify MSHR memory response logic
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2013-04-06 01:03:37 -07:00 |
|
Andrew Waterman
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1abb9277db
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fix LR/SC atomicity violation
note, it's still not starvation-free.
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2013-04-05 19:13:38 -07:00 |
|
Andrew Waterman
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8cbdeb2abf
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add LR/SC support
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2013-04-04 17:07:09 -07:00 |
|
Andrew Waterman
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fc46daecf6
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don't flush pipeline on writes to side-effect-free PCRs
notably, K0, K1, and EPC
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2013-04-04 17:07:09 -07:00 |
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Andrew Waterman
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8b439ef20d
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only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
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2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
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d43f484feb
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take interrupts on nonzero fromhost values
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2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
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d4a3351cfc
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expose pending interrupts in status register
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2013-04-04 17:07:08 -07:00 |
|
Henry Cook
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c6b56c5f25
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bump rocket for coherence bug fix
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2013-04-04 15:52:20 -07:00 |
|
Henry Cook
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f8aebcbf8c
|
fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
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2013-04-04 15:50:29 -07:00 |
|
Henry Cook
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9d5e97d89e
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override io in LogicalNetwork
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2013-03-28 14:10:20 -07:00 |
|
Henry Cook
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b6cc08e8ca
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override io in LogicalNetwork
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2013-03-28 14:09:48 -07:00 |
|
Henry Cook
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16ad8a7e9c
|
Fixes after merge
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2013-03-25 19:14:38 -07:00 |
|
Henry Cook
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67fc09f62e
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Fixes after merge, and always self probe.
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2013-03-25 19:12:19 -07:00 |
|
Henry Cook
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16113a96ba
|
fixes after merge
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2013-03-25 19:09:08 -07:00 |
|
Andrew Waterman
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8e926f8d79
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remove aborts
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2013-03-25 17:01:46 -07:00 |
|
Henry Cook
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eec590c1bf
|
Added support for multiple L2 banks. Moved tile IO queueing.
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2013-03-25 17:01:46 -07:00 |
|
Henry Cook
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806f897fc4
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nTiles -> nClients in LogicalNetworkConfig
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2013-03-25 17:01:46 -07:00 |
|
Andrew Waterman
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ce4c1aa566
|
remove aborts
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2013-03-25 17:01:46 -07:00 |
|
Henry Cook
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cf76665d09
|
writebacks on release network pass asm tests and bmarks
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2013-03-25 17:01:46 -07:00 |
|
Henry Cook
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a0dc8d52d6
|
using new network and l2 controller
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2013-03-25 17:01:46 -07:00 |
|
Andrew Waterman
|
def11e44b8
|
don't pipe stdout to vcd2vpd
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2013-03-25 17:01:13 -07:00 |
|
Andrew Waterman
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ef4927c9ad
|
use a named pipe for VCD -> VPD conversion
|
2013-03-25 16:19:19 -07:00 |
|
Henry Cook
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06f5de3b68
|
Merge branch 'release-xacts'
Conflicts:
src/package.scala
src/uncore.scala
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2013-03-20 17:38:46 -07:00 |
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Henry Cook
|
95f0a688e9
|
Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
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2013-03-20 17:37:50 -07:00 |
|
Henry Cook
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4d007d5c40
|
changed val names in hub to match new tilelink names
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2013-03-20 17:14:07 -07:00 |
|
Henry Cook
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273bd34091
|
Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
|
2013-03-20 15:53:36 -07:00 |
|
Henry Cook
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c36b1dfa30
|
Cleaned up uncore and coherence interface. Removed defunct broadcast hub. Trait-ified tilelink bundle components. Added generalized mem arbiter.
|
2013-03-20 15:52:39 -07:00 |
|
Henry Cook
|
319b4544d7
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-20 14:30:16 -07:00 |
|
Henry Cook
|
a7ae7e5758
|
Cleaned up self-probes
|
2013-03-20 14:28:20 -07:00 |
|
Henry Cook
|
6d2541aced
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-20 14:12:36 -07:00 |
|
Andrew Waterman
|
7b019cb0da
|
rmeove aborts
|
2013-03-19 15:30:23 -07:00 |
|
Andrew Waterman
|
ea9d0b771e
|
remove aborts; simplify probes
|
2013-03-19 15:29:40 -07:00 |
|
Yunsup Lee
|
bc140ce9bc
|
add vec_{vvadd,cmplxmult,matmul} bmarks
|
2013-03-19 00:43:51 -07:00 |
|
Yunsup Lee
|
9efe71412f
|
add DRAMSideLLCNull
|
2013-03-19 00:43:34 -07:00 |
|
Yunsup Lee
|
0f50970913
|
move HellaQueue to uncore
|
2013-03-19 00:43:20 -07:00 |
|
Yunsup Lee
|
f120800aa2
|
add DRAMSideLLCNull
|
2013-03-19 00:41:28 -07:00 |
|
Yunsup Lee
|
717a78f964
|
fix seqRead inference
|
2013-03-19 00:41:09 -07:00 |
|
Henry Cook
|
9f0ccbeac5
|
writebacks on release network pass asm tests and bmarks
|
2013-02-28 18:13:41 -08:00 |
|
Henry Cook
|
e0361840bd
|
writebacks on release network pass asm tests and bmarks
|
2013-02-28 18:11:40 -08:00 |
|
Andrew Waterman
|
944f56a766
|
remove duplicate definitions
|
2013-02-28 14:55:19 -08:00 |
|
Andrew Waterman
|
c6695bee7c
|
fix emulator HTIF interface bug
|
2013-02-20 16:11:21 -08:00 |
|
Andrew Waterman
|
fc26150933
|
update to new Mem style
|
2013-02-20 16:10:47 -08:00 |
|
Andrew Waterman
|
35349d227f
|
update to new Mem style
|
2013-02-20 16:09:46 -08:00 |
|
Eric Love
|
17b8654042
|
Merge branch 'master' of github.com:ucb-bar/reference-chip
|
2013-02-12 12:47:03 -06:00 |
|
Yunsup Lee
|
61b18a6722
|
push rocket,hwacha,uncore
|
2013-02-09 01:05:51 -08:00 |
|
Andrew Waterman
|
9f89c812b7
|
fix HTIF memory size reporting
|
2013-01-29 23:08:25 -08:00 |
|
Yunsup Lee
|
a0bd0adeb2
|
change write/read port ordering for vlsi_mem_gen script
|
2013-01-29 21:32:42 -08:00 |
|
Andrew Waterman
|
66eb3720a4
|
fix SRAM semantics bug in HellaFlowQueue
|
2013-01-29 21:16:42 -08:00 |
|
Yunsup Lee
|
60bd3a6413
|
Revert "shuffled FPU control logic around to make functional unit retiming work better"
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
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2013-01-29 19:34:55 -08:00 |
|