Henry Cook
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dd5052888d
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refactor tilelink params, compiles but ExampleSmallConfig fails
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2015-10-13 23:44:05 -07:00 |
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Howard Mao
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47da284e56
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TileLinkNarrower should do nothing if interfaces are the same width
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2015-10-13 13:28:47 -07:00 |
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Howard Mao
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a44e054c77
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add support for different TileLink and MIF data widths
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2015-10-13 12:46:23 -07:00 |
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Howard Mao
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83df05cb6a
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add TileLink data narrower
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2015-10-13 12:45:39 -07:00 |
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Howard Mao
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2fee3fd0fd
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make sure NASTI -> SMI converter still works if words per beat is 1
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2015-10-13 12:44:48 -07:00 |
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Howard Mao
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993ed86198
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move ReorderQueue to utils.scala
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2015-10-13 09:49:22 -07:00 |
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Henry Cook
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9d11b64c75
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added HasAddrMapParameters and GlobalAddrMap
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2015-10-06 18:24:08 -07:00 |
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Henry Cook
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4508666d96
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log2ceil
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2015-10-06 18:22:47 -07:00 |
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Henry Cook
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8173695800
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added HasAddrMapParameters
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2015-10-06 18:22:40 -07:00 |
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Henry Cook
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166df221ad
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added HasAddrMapParameters
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2015-10-06 18:15:16 -07:00 |
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Henry Cook
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1c489d75c1
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inject params at top-level for MemDessert
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2015-10-06 16:26:58 -07:00 |
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Henry Cook
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c4eadbda57
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Removed all traces of params
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2015-10-06 11:42:06 -07:00 |
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Henry Cook
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38ae2707a3
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refactor MemIO to not use params
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2015-10-06 11:41:48 -07:00 |
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Henry Cook
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3d10a89907
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refactor NASTI to not use param; new AddrMap class
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2015-10-06 11:41:47 -07:00 |
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Henry Cook
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84576650b5
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Removed all traces of params
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2015-10-05 21:48:05 -07:00 |
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Henry Cook
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adcd77db36
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Removed all traces of params
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2015-10-05 20:33:55 -07:00 |
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Henry Cook
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970445a26a
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refactor MemIO to not use params
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2015-10-02 15:37:41 -07:00 |
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Henry Cook
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69a4dd0a79
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refactor NASTI to not use param
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2015-10-02 14:20:47 -07:00 |
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Henry Cook
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39a749843c
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refactor NASTI to not use param; new AddrMap class
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2015-10-02 14:19:51 -07:00 |
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Andrew Waterman
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c2ad0b7dd4
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Unfuck fpga-zynq submodule pointer
Sorry, Scott.
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2015-10-01 15:00:35 -07:00 |
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Andrew Waterman
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996670a4a6
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Point to correct Chisel commit
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2015-10-01 10:31:29 -07:00 |
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Howard Mao
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a76f0bf8fb
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fix involuntary release bug in rocket ProbeUnit
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2015-09-30 17:26:48 -07:00 |
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Howard Mao
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19656e4abe
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make sure to generate release from clean coh state on probe miss
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2015-09-30 16:58:18 -07:00 |
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Andrew Waterman
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8da7be3211
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More Chisel3 compatibility fixes
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2015-09-30 14:37:40 -07:00 |
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Andrew Waterman
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0fe16ac1c0
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Chisel3 compatibility fixes
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2015-09-30 14:37:00 -07:00 |
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Andrew Waterman
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833909a2b5
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Chisel3 compatibility fixes
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2015-09-30 14:36:26 -07:00 |
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Andrew Waterman
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a7c908cb83
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Don't declare Reg inside of when
We haven't yet decided what the Chisel3 semantics for this will be.
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2015-09-30 12:43:36 -07:00 |
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Howard Mao
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2f3d15675c
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fix DataArray writemask in L1D
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2015-09-28 16:02:39 -07:00 |
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Howard Mao
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1e7f656527
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get release block address from inner release
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2015-09-28 15:02:51 -07:00 |
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Andrew Waterman
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79cdf6efc0
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Make perf counters optional
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2015-09-28 13:56:08 -07:00 |
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Andrew Waterman
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f8a7a80644
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Make perf counters optional
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2015-09-28 13:55:23 -07:00 |
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Andrew Waterman
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5e88ead984
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Add pseudo-ops to instructions.scala
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2015-09-28 11:52:27 -07:00 |
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Andrew Waterman
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b93a94597c
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Remove needless control logic
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2015-09-27 13:31:52 -07:00 |
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Howard Mao
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353b00c8a1
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revert some Chisel3-related changes and fix tlb bugs
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2015-09-26 22:08:06 -07:00 |
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Howard Mao
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4bda6b6757
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fix bug in tlb refill
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2015-09-26 21:27:36 -07:00 |
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Howard Mao
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6bf8f41cef
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make sure passthrough requests are treated as vm_enabled = false
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2015-09-26 20:29:51 -07:00 |
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Howard Mao
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c517d9f6e3
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fix htif emulator constructor in vcs_main
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2015-09-25 17:21:09 -07:00 |
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Andrew Waterman
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c3fff12ff0
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Revert "replace remaining uses of Vec.fill"
This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
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2015-09-25 17:09:06 -07:00 |
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Andrew Waterman
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3b1da4c57e
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Revert "replace remaining uses of Vec.fill"
This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
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2015-09-25 17:06:57 -07:00 |
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Andrew Waterman
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20b7a82ab6
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Use Vec.fill, not Vec.apply, when making Vec literals
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2015-09-25 17:06:52 -07:00 |
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Andrew Waterman
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a08872c0e9
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val -> def in static object
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2015-09-25 17:05:28 -07:00 |
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Andrew Waterman
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e75674c0cb
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Revert "replace remaining uses of Vec.fill"
This reverts commit 16dca2186b95945ad2ba5f906113101de0726617.
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2015-09-25 17:05:07 -07:00 |
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Andrew Waterman
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2179cb64ae
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Let isRead be true for store-conditional
This works around a deadlock bug in the L1 D$, and is arguably true.
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2015-09-25 15:28:02 -07:00 |
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Andrew Waterman
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0bfb2962a6
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Assume coh.isRead returns true for store-conditional
This requires an uncore update.
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2015-09-25 15:26:11 -07:00 |
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Howard Mao
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7b0167b92e
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make sure SCR and PCR data width matches xLen
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2015-09-25 12:13:22 -07:00 |
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Howard Mao
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0e67d824b4
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fix NASTI interconnect bug
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2015-09-25 12:12:34 -07:00 |
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Howard Mao
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308022210a
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use updated NASTI channel constructors
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2015-09-25 12:07:27 -07:00 |
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Howard Mao
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8c4ac0f4f3
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make sure CSR/SCR data width matches xLen
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2015-09-25 12:07:03 -07:00 |
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Howard Mao
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a9c6cced2d
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fix bug in NASTIArbiter
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2015-09-25 11:03:24 -07:00 |
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Howard Mao
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2e63fb291a
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put sensible defaults for NASTI channel constructors
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2015-09-25 10:09:25 -07:00 |
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