Henry Cook
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6d61baa6cd
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Initial version of phys/log network compiles
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2012-12-12 11:08:50 -08:00 |
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Henry Cook
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f359518e52
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wip: new network classes
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2012-12-12 11:08:50 -08:00 |
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Andrew Waterman
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05f19b21d0
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merge multiplier and divider
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2012-12-12 02:22:47 -08:00 |
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Andrew Waterman
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c921fc34a9
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merge ALU left and right shifters
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2012-12-12 02:22:34 -08:00 |
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Henry Cook
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be4e5b8327
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Initial version of phys/log network compiles
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2012-12-12 00:06:14 -08:00 |
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Henry Cook
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8d69f9b41c
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Initial version of phys/log network compiles
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2012-12-12 00:05:28 -08:00 |
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Andrew Waterman
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f5c53ce35d
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add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
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2012-12-11 15:58:53 -08:00 |
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Yunsup Lee
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98c0ea9875
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push rocket, tests, and vt-libs
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2012-12-07 16:59:15 -08:00 |
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Andrew Waterman
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3f59e439ef
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fix d$ tag raw hazard
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2012-12-07 15:14:20 -08:00 |
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Henry Cook
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12caa55dc7
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wip: new network classes
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2012-12-06 18:51:30 -08:00 |
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Andrew Waterman
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e9752f1d72
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pipeline host pcr access
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2012-12-06 14:22:07 -08:00 |
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Andrew Waterman
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10a6a42a4a
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make vlsi use dram model by default
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2012-12-06 03:13:45 -08:00 |
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Andrew Waterman
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4dda38204f
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fix d$ reset bug
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2012-12-06 03:13:22 -08:00 |
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Andrew Waterman
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290d3d226c
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fix AMO and store bypass bugs
thanks, torture tester
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2012-12-06 02:07:52 -08:00 |
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Andrew Waterman
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aae7a67781
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fix llc refill/writeback bugs
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2012-12-06 02:07:03 -08:00 |
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Andrew Waterman
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d911e635d6
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simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
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2012-12-04 07:04:26 -08:00 |
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Andrew Waterman
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50e9d952e8
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don't initiate llc refill until writeback drains
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2012-12-04 06:57:53 -08:00 |
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Andrew Waterman
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4608660f6e
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torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
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2012-12-04 05:57:53 -08:00 |
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Andrew Waterman
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5dfb388f03
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update to newest rocket
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2012-11-27 02:43:31 -08:00 |
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Andrew Waterman
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90cae54ac4
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fix D$ read/write concurrency bug
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2012-11-27 02:42:27 -08:00 |
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Andrew Waterman
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9c857b83f0
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refactor PCR file
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2012-11-27 01:28:06 -08:00 |
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Andrew Waterman
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ea7029484e
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update to latest rocket
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2012-11-26 20:57:12 -08:00 |
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Andrew Waterman
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8103676b37
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reduce physical address space to 4GB
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2012-11-26 20:54:56 -08:00 |
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Andrew Waterman
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64674d4d39
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clean up PTW and support PADDR_BITS < VADDR_BITS
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2012-11-26 20:38:45 -08:00 |
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Andrew Waterman
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608f65e716
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don't wastefully read 2x the bits from D$ RAMs
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2012-11-26 20:34:30 -08:00 |
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Andrew Waterman
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352bb464b5
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clock gate X/M and M/W store data registers
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2012-11-26 20:33:41 -08:00 |
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Andrew Waterman
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8a6ff5f9aa
|
fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
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2012-11-25 19:46:48 -08:00 |
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Andrew Waterman
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e12af07722
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update to newest rocket
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2012-11-25 04:40:46 -08:00 |
|
Andrew Waterman
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de2f28193a
|
get rid of more global constants
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2012-11-25 04:24:25 -08:00 |
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Andrew Waterman
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c036cdc1ea
|
add option for 2-cycle load-use delay
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2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
|
b514c7b725
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clean up I$ parity code
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2012-11-24 22:00:43 -08:00 |
|
Andrew Waterman
|
55082e45c4
|
add AVec, which automatically infers element type
should consider modifying Vec as such
|
2012-11-24 18:19:28 -08:00 |
|
Andrew Waterman
|
9372912a9c
|
update to newest rocket
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2012-11-20 05:42:44 -08:00 |
|
Andrew Waterman
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6d47d18c2b
|
catch sigterm to gracefully exit (fixes vcd)
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2012-11-20 05:40:44 -08:00 |
|
Andrew Waterman
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7330deb13a
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print stack trace if elaboration fails
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2012-11-20 05:39:48 -08:00 |
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Andrew Waterman
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56f9b9721d
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treat prefetches as read requests
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2012-11-20 05:38:49 -08:00 |
|
Andrew Waterman
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2b26082132
|
use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
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2012-11-20 04:09:26 -08:00 |
|
Andrew Waterman
|
72f94d1141
|
fix virtual address sign extension detection
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2012-11-20 04:06:57 -08:00 |
|
Andrew Waterman
|
30038bda8a
|
bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
|
2012-11-20 01:33:32 -08:00 |
|
Yunsup Lee
|
4d73e6e38a
|
revamp vector yet again with new D$
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2012-11-18 03:14:22 -08:00 |
|
Yunsup Lee
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6bd4f93f8c
|
pull out prefetch commands from isRead
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2012-11-18 03:13:17 -08:00 |
|
Yunsup Lee
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395e4e3dd6
|
andrew'x fix for D$ corner case in writeback->abort->probe
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2012-11-18 03:11:06 -08:00 |
|
Yunsup Lee
|
06eeb90e2a
|
vector unit interfaces to the new D$
|
2012-11-17 20:07:41 -08:00 |
|
Yunsup Lee
|
81d711e892
|
fix D$ bug; now D$ doesn't respond to prefetches
|
2012-11-17 20:06:13 -08:00 |
|
Andrew Waterman
|
7bcf59a18f
|
support continous compilation via "make test"
for c++ emulator only, for now
|
2012-11-17 19:58:18 -08:00 |
|
Andrew Waterman
|
b58214d7e3
|
remove more global constants
|
2012-11-17 17:25:43 -08:00 |
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
cf05b604b3
|
upgrade to new rocket; improve vlsi makefiles
|
2012-11-17 07:21:29 -08:00 |
|
Andrew Waterman
|
5a7777fe4d
|
clock gate integer datapath more aggressively
|
2012-11-17 06:48:44 -08:00 |
|
Andrew Waterman
|
cc067026a2
|
pipeline D$ response -> FPU regfile
|
2012-11-17 06:48:11 -08:00 |
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