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Initial version of phys/log network compiles

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This commit is contained in:
Henry Cook 2012-12-12 00:05:28 -08:00
parent f359518e52
commit 6d61baa6cd
4 changed files with 77 additions and 78 deletions
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1
uncore/src/memserdes.scala
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@ -4,7 +4,6 @@ import Chisel._
import Node._
import Constants._
import scala.math._
import uncore._
class ioMemSerialized(w: Int) extends Bundle
{

74
uncore/src/package.scala
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@ -1,13 +1,67 @@
package uncore
import uncore.constants._
package object uncore {
import Chisel._
//TODO: When compiler bug SI-5604 is fixed in 2.10, change object Constants to
// package object uncore and remove import Constants._'s from other files
object Constants extends
MemoryOpConstants with
MemoryInterfaceConstants with
CacheConstants with
AddressConstants
{
case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
val src = UFix(width = conf.idBits)
val dst = UFix(width = conf.idBits)
}
abstract class PhysicalNetworkIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends FIFOIO()(data) {
val header = (new PhysicalHeader).asOutput
}
class BasicCrossbarIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetworkIO()(data)(conf)
abstract class PhysicalNetwork(conf: PhysicalNetworkConfiguration) extends Component
class BasicCrossbar[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
val io = new Bundle {
val in = Vec(conf.nEndpoints) { (new BasicCrossbarIO) { data } }.flip
val out = Vec(conf.nEndpoints) { (new BasicCrossbarIO) { data } }
}
for(i <- 0 until conf.nEndpoints) {
val rrarb = new RRArbiter(conf.nEndpoints)(data)
(rrarb.io.in, io.in).zipped.map( (arb, io) => {
arb.valid := io.valid && (io.header.dst === UFix(i))
arb.bits := io.bits
io.ready := arb.ready
})
io.out(i) <> rrarb.io.out
}
}
case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int, nHubs: Int, nTiles: Int)
abstract class LogicalNetwork[TileLinkType <: Bundle](endpoints: Seq[Component])(implicit conf: LogicalNetworkConfiguration) extends Component {
val io: Vec[TileLinkType]
val physicalNetworks: Seq[PhysicalNetwork]
require(endpoints.length == conf.nEndpoints)
}
class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
val src = UFix(width = conf.idBits)
val dst = UFix(width = conf.idBits)
}
abstract class LogicalNetworkIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends FIFOIO()(data) {
val header = (new LogicalHeader).asOutput
}
class TileIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends LogicalNetworkIO()(data)(conf)
class HubIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends LogicalNetworkIO()(data)(conf){flip()}
class TileLink(implicit conf: LogicalNetworkConfiguration) extends Bundle {
val xact_init = (new TileIO) { new TransactionInit }
val xact_init_data = (new TileIO) { new TransactionInitData }
val xact_abort = (new HubIO) { new TransactionAbort }
val probe_req = (new HubIO) { new ProbeRequest }
val probe_rep = (new TileIO) { new ProbeReply }
val probe_rep_data = (new TileIO) { new ProbeReplyData }
val xact_rep = (new HubIO) { new TransactionReply }
val xact_finish = (new TileIO) { new TransactionFinish }
val incoherent = Bool(OUTPUT)
}
}

13
uncore/src/temp.scala Normal file
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@ -0,0 +1,13 @@
package uncore
import _root_.uncore.constants._
//TODO: When compiler bug SI-5604 is fixed in 2.10, remove object Constants and
// mixin Constants traits to package object uncore in package.scala and
// remove import Constants._'s from other .scala files
object Constants extends
MemoryOpConstants with
MemoryInterfaceConstants with
CacheConstants with
AddressConstants
{
}

67
uncore/src/tilelink.scala
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@ -3,73 +3,6 @@ package uncore
import Chisel._
import Constants._
case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
val src = UFix(width = conf.idBits)
val dst = UFix(width = conf.idBits)
}
class BasicCrossbarIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetworkIO()(data)(conf) {
val temp = UFix(width = conf.idBits)
}
abstract class PhysicalNetworkIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends FIFOIO()(data) {
val header = (new PhysicalHeader).asInput
}
abstract class PhysicalNetwork(implicit conf: PhysicalNetworkConfiguration) extends Component
class BasicCrossbar[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
val io = new Bundle {
val in = Vec(conf.nEndpoints) { (new BasicCrossbarIO) { data } }
val out = Vec(conf.nEndpoints) { (new BasicCrossbarIO) { data } }.flip
}
for(i <- 0 until conf.nEndpoints) {
val rrarb = new RRArbiter(conf.nEndpoints)(data)
(rrarb.io.in, io.in).zipped.map( (arb, io) => {
arb.valid := io.valid && (io.header.dst === UFix(i))
arb.bits := io.bits
io.ready := arb.ready
})
io.out(i) <> rrarb.io.out
}
}
case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
abstract class LogicalNetwork[TileLinkType <: Bundle](endpoints: Seq[Component])(implicit conf: LogicalNetworkConfiguration) extends Component {
val io: Vec[TileLinkType]
val physicalNetworks: Seq[PhysicalNetwork]
require(endpoints.length == conf.nEndpoints)
}
class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
val src = UFix(width = conf.idBits)
val dst = UFix(width = conf.idBits)
}
abstract class LogicalNetworkIO[T <: Data]()(data: => T)(implicit m: Manifest[T], conf: LogicalNetworkConfiguration) extends FIFOIO()(data) {
val header = (new LogicalHeader).asInput
}
class TileIO[T <: Data]()(data: => T)(implicit m: Manifest[T], conf: LogicalNetworkConfiguration) extends LogicalNetworkIO()(data)(m,conf)
class HubIO[T <: Data]()(data: => T)(implicit m: Manifest[T], conf: LogicalNetworkConfiguration) extends LogicalNetworkIO()(data)(m,conf)
class TileLink(implicit conf: LogicalNetworkConfiguration) extends Bundle {
val xact_init = (new TileIO) { new TransactionInit }
val xact_init_data = (new TileIO) { new TransactionInitData }
val xact_abort = (new HubIO) { new TransactionAbort }
val probe_req = (new HubIO) { new ProbeRequest }
val probe_rep = (new TileIO) { new ProbeReply }
val probe_rep_data = (new TileIO) { new ProbeReplyData }
val xact_rep = (new HubIO) { new TransactionReply }
val xact_finish = (new TileIO) { new TransactionFinish }
val incoherent = Bool(OUTPUT)
}
class PhysicalAddress extends Bundle {
val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
}