Henry Cook
d29793d1f7
cleanup CoherenceMetadata and coherence params
2014-12-15 19:23:38 -08:00
Andrew Waterman
d04da83f96
Make data RAMs 1RW instead of 1R1W
2014-12-15 17:36:17 -08:00
Henry Cook
6a8b66231c
Add uncached->cached tilelink converter
2014-12-12 17:06:03 -08:00
Henry Cook
424df2368f
1R/W L2 data array?
...
Add TLDataBeats to new LLC; all bmarks pass
2014-12-12 17:05:21 -08:00
Henry Cook
3026c46a9c
Finish adding TLDataBeats to uncore & hub
2014-12-12 17:04:52 -08:00
Henry Cook
2f733a60db
Begin adding TLDataBeats to uncore
2014-12-12 17:04:31 -08:00
Henry Cook
c9320862ae
add l2 dmem signal to rocc
2014-12-12 16:55:08 -08:00
Henry Cook
72ea24283b
multibeat TL; passes all tests
2014-12-12 16:54:33 -08:00
Henry Cook
404773eb9f
fix wb bug
2014-12-03 14:22:39 -08:00
Henry Cook
05b5188ad9
meta and data bundle refactor
2014-11-19 15:55:25 -08:00
Christopher Celio
f19b3ca43e
Deleted extra spaces at EOL in ctrl.scala
2014-11-16 22:04:33 -08:00
Christopher Celio
6749f67b7f
Fixed BHT update error.
...
- separated out BTB/BHT update
- BHT updates counters on every branch
- BTB update only on mispredicted and taken branches
2014-11-16 22:02:27 -08:00
Henry Cook
a519a43f23
Merge branch 'master' into new-llc
...
Conflicts:
src/main/scala/coherence.scala
src/main/scala/memserdes.scala
src/main/scala/tilelink.scala
2014-11-12 16:25:25 -08:00
Henry Cook
cb7e712599
Added uncached write data queue to coherence hub
2014-11-12 12:55:07 -08:00
Henry Cook
b7b2923bff
Cleanup MSHR internal bundles
2014-11-11 18:18:35 -08:00
Henry Cook
82155f333e
Major tilelink revision for uncached message types
2014-11-11 17:36:55 -08:00
Henry Cook
c9e7874818
Major tilelink revision for uncached message types
2014-11-11 17:36:48 -08:00
Henry Cook
35553cc0b7
NullDirectory sharers.count fix
2014-11-11 16:05:25 -08:00
Christopher Celio
fea31d2167
Significant changes and fixes to BTB for superscalar fetch.
...
- BTBUpdate only occurs on mispredicts now.
- RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
Decode).
- Added optional 2nd CAM port to BTB for updates (for when updates to the
BTB may occur out-of-order).
- Fixed resp.mask bit logic.
2014-11-11 03:34:05 -08:00
Henry Cook
bf901e4bca
Remove master_xact_id from Release
2014-11-06 12:09:45 -08:00
Henry Cook
10309849b7
Remove master_xact_id from Probe and Release
2014-11-06 12:07:33 -08:00
Christopher Celio
3be3cd7731
Fixed error with icache/btb resp mask.
2014-11-03 01:13:22 -08:00
Henry Cook
27c72e5eed
nearly all isa tests pass
2014-10-23 21:50:03 -07:00
Henry Cook
a891ba1d46
more correct handling of internal state
2014-10-21 17:40:30 -07:00
Yunsup Lee
170f1fecbc
push chisel,rocket,riscv-tools
2014-10-21 12:32:58 -07:00
Christopher Celio
08d2c13330
Fixed btb/icache bugs regarding resp mask, fw==1
2014-10-20 18:45:23 -07:00
Henry Cook
044b19dbc1
Compiles and elaborates, does not pass asm tests
2014-10-15 11:46:35 -07:00
Christopher Celio
91efdc379b
Merge remote-tracking branch 'origin/master' into ss-frontend
...
Also fixed bridx logic and zero-width wire logic.
Conflicts:
src/main/scala/btb.scala
2014-10-14 18:10:29 -07:00
Andrew Waterman
7bb7299018
Don't pollute BTB with PC+4 target predictions
2014-10-14 17:28:37 -07:00
Henry Cook
86bdbd6535
new tshrs, compiles but does not elaborate
2014-10-07 22:33:10 -07:00
Yunsup Lee
1b31931981
Merge pull request #2 from wasserfuhr/patch-1
...
Update README.md
2014-10-07 17:02:55 -07:00
RainerWasserfuhr
9b41ad92ba
Update README.md
...
typo?
2014-10-08 01:46:48 +02:00
Yunsup Lee
f15baeea49
fix markdown for webpage
2014-10-07 03:55:00 -07:00
Yunsup Lee
5ca7f08226
change rocket submodule
2014-10-07 03:19:48 -07:00
Yunsup Lee
e1b8f69cb5
change submodule pointers to https
2014-10-07 03:16:20 -07:00
Yunsup Lee
447761b06c
fix typo in README
2014-10-07 02:09:34 -07:00
Yunsup Lee
91f211f766
updates to README
2014-10-07 02:08:03 -07:00
Yunsup Lee
702ddabe26
add ExampleSmallConfig for README
2014-10-07 02:07:59 -07:00
Yunsup Lee
ae9b78d9ef
add what/how explanation to README
2014-10-07 02:07:39 -07:00
Scott Beamer
5f55ded723
bump fpga submodule
2014-10-06 13:45:12 -07:00
Scott Beamer
06bc6a45db
move fpga repo to git@ from https
2014-10-06 13:45:09 -07:00
Henry Cook
23ae6893ad
bump chisel
2014-10-06 13:45:03 -07:00
Yunsup Lee
e25d420155
Improve ChiselConfig composability; bump chisel
2014-10-06 13:43:40 -07:00
Yunsup Lee
73eac94a65
Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
2014-10-06 13:40:35 -07:00
Henry Cook
f97a801d60
Parameter API update
2014-10-06 13:37:42 -07:00
Henry Cook
122733b3a9
file name consistency
2014-10-06 13:37:38 -07:00
Henry Cook
a9d72aac2a
bump rocket
2014-10-06 13:37:27 -07:00
Henry Cook
0b5f23a209
Streamlined uncore for release
2014-10-06 13:37:15 -07:00
Christopher Celio
59eb7d194d
Finalize superscalar btb.
2014-10-03 16:08:08 -07:00
Andrew Waterman
cde7c9d869
simplify CSR decoding code
2014-10-03 14:31:26 -07:00