riscv/rocket-chip
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141 Commits

Author SHA1 Message Date
Henry Cook 63bd0b9d2a Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed. 2014-08-08 12:27:47 -07:00
Adam Izraelevitz 08d81d0892 First cut at using new chisel parameters for toplevel parameters and fpu 2014-08-01 18:09:37 -07:00
Henry Cook 434da22283 Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel) 2014-05-28 17:16:49 -07:00
Henry Cook b0ccb88982 make outer cache type choice a top-level const 2014-05-28 14:46:07 -07:00
Henry Cook ce056b4b89 client/master -> inner/outer 2014-04-29 16:50:30 -07:00
Henry Cook 224e286dd3 New uncore config objects. Backends get their own file. Simplify fpga uncore. 2014-04-26 19:46:11 -07:00
Henry Cook 3d4273954a TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:19:25 -07:00
Henry Cook fbf6e44376 fix connection error in fpga uncore 2014-04-24 11:58:59 -07:00
Henry Cook cfd6748318 patches to make FAME1/dram IOs compile with up-to-date chisel (bumped) 2014-04-21 17:26:33 -07:00
Henry Cook 2cb4dbae39 Refactored uncore constants and tilelink data 2014-04-10 13:19:50 -07:00
Henry Cook 5a5f69bfca finished uncore constant/tilelink data refactor 2014-04-10 13:13:46 -07:00
Andrew Waterman 817517c663 Better branch prediction 2014-04-07 16:08:06 -07:00
Henry Cook 56f515c255 first steps in uncore constant/tilelink data refactor 2014-03-30 09:21:08 -07:00
Andrew Waterman d055c0ebaf Push rocket/hardfloat/chisel 2014-03-04 16:39:06 -08:00
Yunsup Lee e20d50436a committed in the wrong directory, meant to commit in the hwacha directory 2014-03-01 00:01:35 -08:00
Yunsup Lee 8c459df3b6 flush deck when xcpt occurs, fixes remaining p test bugs 2014-02-28 22:50:34 -08:00
Stephen Twigg 755293d785 Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha). 2014-02-14 10:12:09 -08:00
Andrew Waterman 11e69a73cd Fix tests when !hwacha; disable hwacha by default 2014-02-06 03:08:33 -08:00
Stephen Twigg 8c96e27ca6 Merge branch 'master' into hwacha-port 
Mostly Stable version that is passing tests
 2014-02-04 17:20:28 -08:00
Henry Cook 382fa0ef27 cleanups supporting uncore hierarchy 2014-01-31 16:03:58 -08:00
Stephen Twigg e7ee94bcc8 Merge branch 'master' into hwacha-port 2014-01-21 15:23:05 -08:00
Stephen Twigg ee0c4ca291 Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations) 2014-01-21 14:48:04 -08:00
Andrew Waterman 6f028b2d52 Increase BTB size; fix Rocket FPU bug 2014-01-17 03:53:08 -08:00
Andrew Waterman a43cf9d688 Update to new privileged ISA 2013-11-25 04:45:06 -08:00
Stephen Twigg e50c5180cd Merge branch 'master' into hwacha 2013-11-14 16:03:55 -08:00
Yunsup Lee 1d6d4b4e96 move htif to uncore 2013-11-07 13:19:19 -08:00
Yunsup Lee c810847761 hookup all memory ports 2013-11-05 17:12:25 -08:00
Stephen Twigg 7da65434ee Initial commit for the hwacha reference-chip/rocket re-integration. 2013-10-30 20:44:02 -07:00
Stephen Twigg 36dfff5ee8 Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy. 2013-09-25 01:21:41 -07:00
Andrew Waterman b7d7ced41b Update to new ISA 2013-09-21 06:40:23 -07:00
Huy Vo 09247c0e0b fix to sram init pins 2013-09-19 20:12:10 -07:00
Andrew Waterman 80003b3019 Support RoCC 2013-09-15 04:25:26 -07:00
Andrew Waterman fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
Henry Cook b42e140e05 NetworkIOs no longer use thunks 2013-09-10 16:23:52 -07:00
Stephen Twigg 6cde69e95d Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc. 2013-09-09 14:31:18 -07:00
Yunsup Lee ba9bbc27df apply same change to fpga top-level 2013-08-24 15:50:03 -07:00
Yunsup Lee 76cd90fc01 parameterize number of SCRs 2013-08-24 15:47:42 -07:00
Yunsup Lee 0884bc9789 fix DRAMSideLLCNull entries 2013-08-24 13:20:38 -07:00
Yunsup Lee 1e3ac0afa9 back to NTILES=1 2013-08-24 13:10:30 -07:00
Henry Cook b06d33da2f Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes 2013-08-19 19:54:41 -07:00
Henry Cook 85e5ce046f pulled submodule commits, uncore sbt standardized 2013-08-15 17:07:13 -07:00
Henry Cook 6b20556661 Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 
Conflicts:
	chisel
	riscv-hwacha
	riscv-rocket
	uncore
 2013-08-15 16:39:30 -07:00
Henry Cook 784e017bae Final Reg standardization 2013-08-15 16:37:58 -07:00
Henry Cook 9b70ecf546 Reg standardization 2013-08-13 17:53:19 -07:00
Huy Vo cc6631ae4d reset -> _reset 2013-08-12 20:52:55 -07:00
Henry Cook 11e131af47 initial attempt at upgrade 2013-08-12 10:46:22 -07:00
Henry Cook 199e76fc77 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:31:27 -07:00
Henry Cook 4d916b56e3 Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00
Henry Cook 2796de01bf new tilelink arbiter types, reduced release xact trackers 2013-07-09 15:41:27 -07:00
Henry Cook 896179cbb6 removed bad mt test 2013-06-14 00:14:18 -07:00