riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

hookup all memory ports

This commit is contained in:
Yunsup Lee 2013-11-05 17:12:25 -08:00
parent 3cdfde9861
commit c810847761
2 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket

@ -1 +1 @@
Subproject commit b246050b7de0d5610e59ec9dbdd3839759e354f9
Subproject commit 02da61cc09e674ca9a5f9baaeac580d30cf7d693

3
src/main/scala/RocketChip.scala
View File

@ -254,7 +254,8 @@ class Top extends Module {
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val hc = hwacha.HwachaConfiguration(8, 256)
val vic = ICacheConfig(128, 1)
val hc = hwacha.HwachaConfiguration(vic, 8, 256, ndtlb = 8, nptlb = 2)
val rc = RocketConfiguration(tl, ic, dc,
fpu = HAS_FPU,
rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))