Henry Cook
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63bd0b9d2a
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Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
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2014-08-08 12:27:47 -07:00 |
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Adam Izraelevitz
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08d81d0892
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First cut at using new chisel parameters for toplevel parameters and fpu
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2014-08-01 18:09:37 -07:00 |
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Henry Cook
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434da22283
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Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)
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2014-05-28 17:16:49 -07:00 |
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Henry Cook
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b0ccb88982
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make outer cache type choice a top-level const
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2014-05-28 14:46:07 -07:00 |
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Henry Cook
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ce056b4b89
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client/master -> inner/outer
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2014-04-29 16:50:30 -07:00 |
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Henry Cook
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224e286dd3
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New uncore config objects. Backends get their own file. Simplify fpga uncore.
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2014-04-26 19:46:11 -07:00 |
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Henry Cook
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3d4273954a
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TileLinkIO.GrantAck -> TileLinkIO.Finish
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2014-04-26 15:19:25 -07:00 |
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Henry Cook
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fbf6e44376
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fix connection error in fpga uncore
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2014-04-24 11:58:59 -07:00 |
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Henry Cook
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cfd6748318
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patches to make FAME1/dram IOs compile with up-to-date chisel (bumped)
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2014-04-21 17:26:33 -07:00 |
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Henry Cook
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2cb4dbae39
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Refactored uncore constants and tilelink data
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2014-04-10 13:19:50 -07:00 |
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Henry Cook
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5a5f69bfca
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finished uncore constant/tilelink data refactor
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2014-04-10 13:13:46 -07:00 |
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Andrew Waterman
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817517c663
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Better branch prediction
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2014-04-07 16:08:06 -07:00 |
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Henry Cook
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56f515c255
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first steps in uncore constant/tilelink data refactor
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2014-03-30 09:21:08 -07:00 |
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Andrew Waterman
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d055c0ebaf
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Push rocket/hardfloat/chisel
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2014-03-04 16:39:06 -08:00 |
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Yunsup Lee
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e20d50436a
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committed in the wrong directory, meant to commit in the hwacha directory
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2014-03-01 00:01:35 -08:00 |
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Yunsup Lee
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8c459df3b6
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flush deck when xcpt occurs, fixes remaining p test bugs
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2014-02-28 22:50:34 -08:00 |
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Stephen Twigg
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755293d785
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Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha).
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2014-02-14 10:12:09 -08:00 |
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Andrew Waterman
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11e69a73cd
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Fix tests when !hwacha; disable hwacha by default
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2014-02-06 03:08:33 -08:00 |
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Stephen Twigg
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8c96e27ca6
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Merge branch 'master' into hwacha-port
Mostly Stable version that is passing tests
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2014-02-04 17:20:28 -08:00 |
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Henry Cook
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382fa0ef27
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cleanups supporting uncore hierarchy
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2014-01-31 16:03:58 -08:00 |
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Stephen Twigg
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e7ee94bcc8
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Merge branch 'master' into hwacha-port
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2014-01-21 15:23:05 -08:00 |
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Stephen Twigg
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ee0c4ca291
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Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations)
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2014-01-21 14:48:04 -08:00 |
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Andrew Waterman
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6f028b2d52
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Increase BTB size; fix Rocket FPU bug
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2014-01-17 03:53:08 -08:00 |
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Andrew Waterman
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a43cf9d688
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Update to new privileged ISA
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2013-11-25 04:45:06 -08:00 |
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Stephen Twigg
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e50c5180cd
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Merge branch 'master' into hwacha
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2013-11-14 16:03:55 -08:00 |
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Yunsup Lee
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1d6d4b4e96
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move htif to uncore
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2013-11-07 13:19:19 -08:00 |
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Yunsup Lee
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c810847761
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hookup all memory ports
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2013-11-05 17:12:25 -08:00 |
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Stephen Twigg
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7da65434ee
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Initial commit for the hwacha reference-chip/rocket re-integration.
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2013-10-30 20:44:02 -07:00 |
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Stephen Twigg
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36dfff5ee8
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Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy.
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2013-09-25 01:21:41 -07:00 |
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Andrew Waterman
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b7d7ced41b
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Update to new ISA
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2013-09-21 06:40:23 -07:00 |
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Huy Vo
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09247c0e0b
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fix to sram init pins
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2013-09-19 20:12:10 -07:00 |
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Andrew Waterman
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80003b3019
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Support RoCC
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2013-09-15 04:25:26 -07:00 |
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Andrew Waterman
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fbdbb01232
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update to new isa; disable vector tests
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2013-09-12 17:04:03 -07:00 |
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Henry Cook
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b42e140e05
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NetworkIOs no longer use thunks
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2013-09-10 16:23:52 -07:00 |
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Stephen Twigg
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6cde69e95d
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Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
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2013-09-09 14:31:18 -07:00 |
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Yunsup Lee
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ba9bbc27df
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apply same change to fpga top-level
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2013-08-24 15:50:03 -07:00 |
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Yunsup Lee
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76cd90fc01
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parameterize number of SCRs
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2013-08-24 15:47:42 -07:00 |
|
Yunsup Lee
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0884bc9789
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fix DRAMSideLLCNull entries
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2013-08-24 13:20:38 -07:00 |
|
Yunsup Lee
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1e3ac0afa9
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back to NTILES=1
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2013-08-24 13:10:30 -07:00 |
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Henry Cook
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b06d33da2f
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Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
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2013-08-19 19:54:41 -07:00 |
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Henry Cook
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85e5ce046f
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pulled submodule commits, uncore sbt standardized
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2013-08-15 17:07:13 -07:00 |
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Henry Cook
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6b20556661
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Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2
Conflicts:
chisel
riscv-hwacha
riscv-rocket
uncore
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2013-08-15 16:39:30 -07:00 |
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Henry Cook
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784e017bae
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Final Reg standardization
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2013-08-15 16:37:58 -07:00 |
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Henry Cook
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9b70ecf546
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Reg standardization
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2013-08-13 17:53:19 -07:00 |
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Huy Vo
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cc6631ae4d
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reset -> _reset
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2013-08-12 20:52:55 -07:00 |
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Henry Cook
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11e131af47
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initial attempt at upgrade
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2013-08-12 10:46:22 -07:00 |
|
Henry Cook
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199e76fc77
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:31:27 -07:00 |
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Henry Cook
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4d916b56e3
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Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file.
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2013-07-24 23:28:43 -07:00 |
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Henry Cook
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2796de01bf
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new tilelink arbiter types, reduced release xact trackers
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2013-07-09 15:41:27 -07:00 |
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Henry Cook
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896179cbb6
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removed bad mt test
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2013-06-14 00:14:18 -07:00 |
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