riscv/rocket-chip
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113 Commits

Author SHA1 Message Date
Henry Cook
3f070eee1f first cut of merging puts/gets 2015-03-17 13:09:44 -07:00
Henry Cook
6af48e168a cleanup mergeData buffer 2015-03-17 13:08:14 -07:00
Henry Cook
1471d9debc fix assert 2015-03-17 05:40:05 -07:00
Yunsup Lee
0e51fef200 bugfix where an in-progress acquire can be blocked by another acquire tracker being free'd up in between 2015-03-17 05:37:56 -07:00
Henry Cook
ce9d4b6e70 further amo cleanups 2015-03-17 05:37:41 -07:00
Henry Cook
f35a6a574f Add a queue on released data coming in to L2 2015-03-16 13:25:01 -07:00
Henry Cook
b72230a9f0 PutBlock bugfix 2015-03-16 00:09:55 -07:00
Henry Cook
23a6b007c1 Fix BroadcastHub AcquiteTracker allocation bug and clean up tracker wiring 2015-03-15 23:10:51 -07:00
Henry Cook
8181262419 clean up incoherent and probe flags 2015-03-12 16:22:14 -07:00
Yunsup Lee
2c31ed6426 previous bug fix for meta data writeback wasn't quite right 2015-03-12 15:34:20 -07:00
Yunsup Lee
5e40c8ba77 write back meta data when cache miss even when coherence meta data is clean 2015-03-12 14:36:46 -07:00
Henry Cook
059575c334 cleanup mergeData and prep for cleaner data_buffer in L2 2015-03-11 15:43:41 -07:00
Yunsup Lee
3ab1aca7de L2 subblock access bugfix 2015-03-11 01:56:47 -07:00
Henry Cook
17072a0041 L2 Writeback bugfix 2015-03-10 01:15:03 -07:00
Henry Cook
002f1a1b39 pin outer finish header 2015-03-09 12:40:37 -07:00
Henry Cook
1bed6ea498 New metadata-based coherence API 2015-02-28 17:32:03 -08:00
Henry Cook
0a8722e881 bugfix for indexing DataArray of of small L2 2015-02-17 00:37:40 -08:00
Henry Cook
0c66e70f14 cleanup of conflicts; allocation bugfix 2015-02-06 13:20:44 -08:00
Henry Cook
7b86ea17cf rename L2HellaCache to L2HellaCacheBank 2015-02-03 19:38:01 -08:00
Stephen Twigg
3b3250339a Explicitely convert results of Bits Muxes to UInt 
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
 2015-02-03 18:15:01 -08:00
Henry Cook
6141b3efc5 uncached -> builtin_type 2015-02-02 01:02:06 -08:00
Henry Cook
e6491d351f Offset AMOs within beat and return old value 2015-02-02 00:22:21 -08:00
Henry Cook
3aa030f960 Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor. 2015-02-01 20:37:16 -08:00
Henry Cook
7b4e9dd137 Block L2 transactions on the same set from proceeding in parallel 2015-02-01 20:29:23 -08:00
Henry Cook
973eb43128 state machine bug on uncached write hits 2015-02-01 20:29:23 -08:00
Henry Cook
f58f8bf385 Make L2 data array use a single Mem 2015-01-25 15:37:04 -08:00
Henry Cook
9ef00d187f %s/master/manager/g + better comments 2014-12-29 22:55:58 -08:00
Henry Cook
e62c71203e disconnect unused outer network headers 2014-12-22 18:50:37 -08:00
Henry Cook
2ef4357ca8 acquire allocation bugfix 2014-12-19 17:39:23 -08:00
Henry Cook
f234fe65ce Initial verison of L2WritebackUnit, passes MiT2 bmark tests 2014-12-19 03:03:53 -08:00
Henry Cook
d121af7f94 Simplify release handling 2014-12-18 17:12:29 -08:00
Henry Cook
bfcfc3fe18 refactor cache params 2014-12-17 14:28:14 -08:00
Henry Cook
ab39cbb15d cleanup DirectoryRepresentation and coherence params 2014-12-15 19:24:42 -08:00
Andrew Waterman
d04da83f96 Make data RAMs 1RW instead of 1R1W 2014-12-15 17:36:17 -08:00
Henry Cook
424df2368f 1R/W L2 data array? 
Add TLDataBeats to new LLC; all bmarks pass
 2014-12-12 17:05:21 -08:00
Henry Cook
3026c46a9c Finish adding TLDataBeats to uncore & hub 2014-12-12 17:04:52 -08:00
Henry Cook
404773eb9f fix wb bug 2014-12-03 14:22:39 -08:00
Henry Cook
05b5188ad9 meta and data bundle refactor 2014-11-19 15:55:25 -08:00
Henry Cook
a519a43f23 Merge branch 'master' into new-llc 
Conflicts:
	src/main/scala/coherence.scala
	src/main/scala/memserdes.scala
	src/main/scala/tilelink.scala
 2014-11-12 16:25:25 -08:00
Henry Cook
27c72e5eed nearly all isa tests pass 2014-10-23 21:50:03 -07:00
Henry Cook
a891ba1d46 more correct handling of internal state 2014-10-21 17:40:30 -07:00
Henry Cook
044b19dbc1 Compiles and elaborates, does not pass asm tests 2014-10-15 11:46:35 -07:00
Henry Cook
86bdbd6535 new tshrs, compiles but does not elaborate 2014-10-07 22:33:10 -07:00
Henry Cook
394eb38a96 temp; converted voluntary wb tracker 2014-10-03 01:06:49 -07:00
Henry Cook
dc1a61264d initial version, acts like old hub 2014-10-03 01:06:49 -07:00
Henry Cook
7571695320 Removed broken or unfinished modules, new MemPipeIO converter 2014-09-24 15:11:24 -07:00
Henry Cook
82fe22f958 support for multiple tilelink paramerterizations in same design 
Conflicts:

	src/main/scala/cache.scala
 2014-09-24 11:30:40 -07:00
Henry Cook
53b8d7b031 use new coherence methods in l2, ready to query dir logic 2014-09-20 18:01:14 -07:00
Henry Cook
149d51d644 more coherence API cleanup 2014-09-20 16:57:13 -07:00
Yunsup Lee
0b51d70bd2 add LICENSE 2014-09-12 15:31:38 -07:00
Henry Cook
dc5643b12f Final parameter refactor. 2014-08-23 01:19:36 -07:00
Henry Cook
e26f8a6f6a Fix errors in derived cache params 2014-08-12 14:55:44 -07:00
Henry Cook
9ab3a4262c Cache utility traits. Completely compiles, asm tests hang. 2014-08-11 18:35:49 -07:00
Henry Cook
f411fdcce3 Full conversion to params. Compiles but does not elaborate. 2014-08-08 12:21:57 -07:00
Henry Cook
3c329df7e7 refactor Metadata, clean and expand coherence API 2014-05-28 13:35:08 -07:00
Henry Cook
0e39346a12 L2-specific metadataarray wrapper, hookups to tshrfile 2014-05-07 01:51:46 -07:00
Henry Cook
bc3ef1011e correct use of function value to initialize MetaDataArray 2014-05-06 12:59:45 -07:00
Henry Cook
45172f1f37 parameterize metadataarray 2014-05-01 01:44:59 -07:00
Henry Cook
0237229921 client/master -> inner/outer 2014-04-29 16:49:18 -07:00
Henry Cook
52c6de5641 DRAMSideLLCLike trait. TSHRFile. New L2 config objects. 2014-04-26 19:11:36 -07:00
Henry Cook
1163131d1e TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:17:05 -07:00
Henry Cook
f8f29c69b8 MetaData & friends moved to uncore/ 2014-04-23 16:24:20 -07:00
Henry Cook
39681303b8 beginning of l2 cache 2014-04-22 16:58:15 -07:00