b43a85e2e8
Make ExampleSmallConfig/DefaultRV32Config smaller
2016-04-01 18:18:08 -07:00
6878e3265f
Default RowBits to TileLink width, not XLen
2016-04-01 18:18:08 -07:00
46d7dceb1e
Disable printf/assert during reset
2016-04-01 18:18:08 -07:00
cd9e07d8e7
Update sbt to 0.13.11
2016-04-01 18:18:08 -07:00
bd3dba7f66
Fix LR/SC livelock bug
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Closes #74 .
2016-04-01 18:18:08 -07:00
35d02c5096
LRSC fix. RocketChipNetwork moved to uncore.
2016-04-01 18:09:00 -07:00
5337c7d22d
add more complicated memtests to travis
2016-03-31 18:42:14 -07:00
4f06a5ff6b
add memtest config for testing memory channel mux
2016-03-31 18:41:56 -07:00
5a74a9b1e7
switch memory interconnect from AXI to TileLink
2016-03-31 18:18:30 -07:00
6d5c98da7d
point submodule pointer to proper commit hash
2016-03-31 15:03:33 -07:00
7c3b57b8fa
switch MMIO network to TileLink
2016-03-31 14:30:10 -07:00
ab540d536a
bump uncore for split metadata chisel3 fix
2016-03-30 22:11:45 -07:00
c831a0a4e5
use scala firrtl instead of stanza firrtl
2016-03-30 19:35:25 -07:00
be612e3843
bump rocket and uncore
2016-03-30 19:23:19 -07:00
c081a36893
Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter"
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This reverts commit 5378f79b50
2016-03-30 19:06:32 -07:00
e77900f540
Revert "switch back to Chisel2 for verilog build for now"
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This reverts commit 3673365b08
2016-03-30 19:00:38 -07:00
8e601f26e1
switch back to the correct chisel3 and firrtl branches
2016-03-30 18:59:33 -07:00
1e03408323
get rid of mt benchmark suite
2016-03-29 20:16:07 -07:00
cf716fea58
fix mm_dramsim2
2016-03-29 20:16:07 -07:00
3673365b08
switch back to Chisel2 for verilog build for now
2016-03-29 20:16:07 -07:00
265a82427e
add DefaultL2Config and DualCoreConfig to travis
2016-03-29 20:16:07 -07:00
ad93e0226d
Changes to prepare for switch to TileLink interconnect
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We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.
* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
2016-03-29 20:16:07 -07:00
5378f79b50
Bump chisel3 and firrtl, add support for firrtl $ delimiter
2016-03-29 20:16:07 -07:00
38649bd4c1
some edits to groundtest regression tests
2016-03-29 20:16:07 -07:00
9b9c662952
fix w_last wire
2016-03-29 20:16:07 -07:00
2b61f28356
don't test DMA controller for now
2016-03-29 20:16:07 -07:00
e1a03cc9ac
fix issue with partial writemasks
2016-03-29 20:16:07 -07:00
6c48dc3471
Use more sensible knob values for SmallConfig
2016-03-25 14:18:24 -07:00
cce89f5fbc
Bump rocket
2016-03-25 14:18:15 -07:00
d1639416cb
Merge pull request #77 from ucb-bar/chisel3
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Preliminary Chisel 3 Support
2016-03-24 12:56:36 -07:00
39cf945efb
Use Chisel 3 to build verilog on Travis
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Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip. We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
2016-03-24 12:00:13 -07:00
cddfdf0929
Add CHISEL_VERSION make argument
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This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
d697559754
Correct the polarity of the non-backup-memory HTIF
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This fails in FIRRTL because <> has polarity now.
2016-03-24 12:00:13 -07:00
7d5eac189b
Bump the uncore for some Chisel3 fixes
2016-03-24 12:00:13 -07:00
4744deec28
Fix the SCR file for Chisel 3
2016-03-24 12:00:13 -07:00
476db6ef39
Move to a newer Scala version
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Chisel3 needs a newer version of Scala to run correctly.
2016-03-24 12:00:13 -07:00
6da45e7f26
Trace generator: updates and additions to the scripts directory.
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(1) Introduce tracegen.py, a script that invokes the emulator (built
with TraceGenConfig), sending a SIGTERM once all cores are finished.
(2) Update toaxe.py to gather some statistics about the trace.
(3) Introduce tracestats.py, which displays the stats in a useful way.
(4) Introduce tracegen+check.py, a top-level script that generates
traces, checks them, and emits stats. If this commit is pulled, it
should be done after pulling my latest groundtest commit.
2016-03-21 15:28:15 -07:00
c989ec5813
Fix the SCR file for Chisel 3
2016-03-21 11:55:40 -07:00
b5992186df
include top-level makefrag in regressions
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fixes issue with rocketchip_addons inclusion
2016-03-16 15:52:28 -07:00
e90a9dfb2b
make taking max of multiple integers in config a bit easier
2016-03-16 14:35:08 -07:00
4fc2a14a63
Fix MIF bug that cuts off upper xact id bits
2016-03-16 13:50:30 -07:00
9dc0cbdfa4
WIP on privileged spec v1.9
2016-03-14 18:03:33 -07:00
648437e7cb
Merge pull request #70 from ucb-bar/add-rv32-support
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Add RV32 test/configuration options
2016-03-14 17:06:39 -07:00
f2ded2721d
Merge branch 'master' into add-rv32-support
2016-03-10 19:33:04 -08:00
25091003af
Add RV32 test/configuration options
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These won't actually work until further commits. Rocket RV32 support
is complete, but on the priv-1.9 branch.
2016-03-10 17:40:21 -08:00
67ad36d74a
Merge pull request #69 from ucb-bar/fix-tabs
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tabs are evil
2016-03-10 16:17:46 -08:00
7a75a03123
tabs are evil
2016-03-10 14:18:56 -08:00
3c9e63f5a5
don't make HTIF clock divider tied to backup memory
2016-03-09 14:58:20 -08:00
5e145515e1
fix some Chisel assertions
2016-03-02 14:50:49 -08:00
9c7e5bc6c0
bump hardfloat, tools(tests & spike) for fcvt fix
2016-03-01 19:53:26 -08:00
Andrew Waterman
Henry Cook
Howard Mao
jackkoenig
Andrew Waterman
Palmer Dabbelt
Palmer Dabbelt
Matthew Naylor
Colin Schmidt
Eric Love