ece3ab9c3d
Refactor AddrMap and its usage ( #122 )
2016-06-03 17:29:05 -07:00
c8338ad809
Instantiate Debug Module ( #119 )
2016-06-02 10:53:41 -07:00
1311e78d3f
Add blocking D$ flush support
2016-05-31 19:28:41 -07:00
50e3caef36
get rid of Zscale file I missed last time
2016-05-31 14:33:38 -07:00
44a216038f
Use more generic TileLinkWidthAdapter
2016-05-27 13:38:13 -07:00
10f0e13c25
Use more parsimonious queue depths
2016-05-26 18:04:22 -07:00
3cc236e9c4
By default, use same TileLink width everywhere
...
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
2016-05-26 18:04:01 -07:00
976d4d3184
ahb: AHB parameters should match TileLink parameters by default
...
Closes #116
2016-05-25 18:01:25 -07:00
ec0d178010
Support M-mode-only implementations
2016-05-25 15:40:53 -07:00
da105a5944
Don't allow travis to recurse through submodules
2016-05-25 13:27:49 -07:00
da566e7d6a
build: use local sbt when building firrtl
2016-05-25 11:48:03 -07:00
e82c080c3c
Add blocking D$
2016-05-25 11:09:50 -07:00
a8462d3cfc
bump chisel
2016-05-25 11:09:50 -07:00
f52fc655a5
remove zscale
2016-05-19 09:43:15 -07:00
abb0e2921b
return non-zero exit codes when an assertion fires
...
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
2016-05-18 12:57:58 -07:00
b396c68577
bump torture for priv-1.9 test-env
2016-05-17 22:02:38 -07:00
b0ae003981
add firrtl to regression makefile
...
this makes it easier to test chisel3 builds
e.g. the local buildbot can now test a bunch of configs
2016-05-17 17:34:20 -07:00
684d902059
Fix PLIC instantiation when S-mode is disabled
2016-05-13 11:22:46 -07:00
6aa708bcee
Disable MMIO by default to avoid disconnected nets
2016-05-11 13:12:39 -07:00
3fe00ce32a
Update README.md
...
- Removed instruction to checkout riscv-tests (as they are now globally installed when building the riscv-tools).
- Clarified the riscv-tools set-up information to clarify that the rocket-chip/riscv-tools is the version to build.
2016-05-10 22:12:02 -07:00
fbff46d27d
bump rocket
2016-05-10 10:57:03 -07:00
aac89ca1f0
Add PLIC
2016-05-10 00:27:31 -07:00
df479d7935
don't make MIFTagBits a computed parameter
2016-05-08 11:04:58 -07:00
3b0e9167fa
add AXI to AHB converter and more conformant HASTI RAM
2016-05-06 11:32:03 -07:00
a875eb9c31
update riscv-tools for bbl fix
2016-05-05 19:36:34 -07:00
18ffe7b1ec
don't use +verbose in vsim .run rule
2016-05-04 23:01:14 -07:00
8b06947446
Run bmarks faster (hopefully)
2016-05-04 22:47:34 -07:00
f1baa4aecc
update riscv-tests so that mm benchmark doesn't run forever
2016-05-04 21:28:55 -07:00
dfcb73b6c9
groundtest only needs to write to a single tohost
2016-05-03 20:21:13 -07:00
4045a07eda
Remove need for separate riscv-tests for groundtest
2016-05-03 18:29:46 -07:00
8f891437b5
fix CacheFillTest
2016-05-03 14:57:05 -07:00
15f4af19cf
Remove HTIF CPU port
2016-05-03 13:55:59 -07:00
487d0b356e
fixes to get groundtest working with priv-1.9 changes
2016-05-03 13:09:44 -07:00
c7c8ae5468
Instantiate PRCI block
2016-05-02 18:08:33 -07:00
6d1e82bddf
Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port
2016-05-02 15:21:55 -07:00
c4d2d29e80
Stub out debug module, rather than leaving it floating
2016-04-30 22:37:39 -07:00
46bbbba5e6
New address map
2016-04-30 20:59:36 -07:00
d0aa4c722d
More WIP on new memory map
2016-04-28 16:15:31 -07:00
1f211b37df
WIP on new memory map
2016-04-27 14:57:54 -07:00
48170fd9aa
add default cases to configs that use CDEMatchError
...
this avoids filling in the stack trace every time
a config doesn't contain the parameter
2016-04-22 12:14:58 -07:00
f7af908969
put memory into the address map and no longer use MMIOBase
2016-04-21 18:53:16 -07:00
325d3671c4
add write data id field for AXI3 compat
2016-04-20 09:21:43 -07:00
0cf6b1f118
merge ATOS changes from hurricane
2016-04-20 09:21:43 -07:00
c19931ba03
add technical report to readme
2016-04-19 16:17:50 -07:00
4afc9c69a0
streamline sbt
2016-04-19 14:22:22 -07:00
7c33d88861
Merge pull request #90 from ucb-bar/elaborate-once
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Bump Chisel3, to elaborate circuits once
2016-04-18 21:04:55 -07:00
85c86994a0
Bump Chisel3, to elaborate circuits once
2016-04-18 14:54:17 -07:00
cbfd7fd13a
Remove tracegen scripts, now in groundtest
...
And bump groundtest.
2016-04-14 14:01:48 -07:00
c5838dd9b3
Fix narrow read/write behavior for AXI converters and fix L2 bugs
...
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.
There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.
There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
c4c6bd1040
Bump rocket.
...
Closes #84 .
2016-04-01 18:20:32 -07:00
Andrew Waterman
Andrew Waterman
Howard Mao
Wesley W. Terpstra
Colin Schmidt
Christopher Celio
Scott Beamer
Yunsup Lee
Palmer Dabbelt
Matthew Naylor