riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman f8bb67ab8f Bind some Make vars early to avoid redundant evaluation 2016-10-28 11:56:13 -07:00
Andrew Waterman f3c726033a Make all Chisel invocations depend on FIRRTL_JAR 2016-10-28 11:56:05 -07:00
Andrew Waterman 2b65478f3a bump chisel/firrtl 2016-10-28 00:36:53 -07:00
Andrew Waterman e45b41b4b6 Don't rely on SeqMem output after read-enable is low 2016-10-27 23:44:10 -07:00
Andrew Waterman 190a8b9dd3 Update README.md to reflect firrtl and riscv-tools changes 2016-10-27 11:40:09 -07:00
Andrew Waterman 0af2a5ba02 bump tools 2016-10-09 22:15:55 -07:00
Andrew WatermanandYunsup Lee 53360f4c2c Disable U-mode by default unless S-mode is present 2016-10-08 21:29:40 -07:00
Andrew WatermanandYunsup Lee 7f429e8799 Simplify AsyncResetReg 
No need for AsyncSetReg, as AsyncResetReg can be used exclusively with
inverted inputs.
 2016-10-08 21:29:40 -07:00
Andrew Waterman 4fd03ffdf1 Fix PopCountAtLeast, un-breaking BTB 2016-10-07 21:20:40 -07:00
Andrew Waterman b1c777c7a2 Fix PLIC enable bit access for #ints >= tlDataBits 2016-10-06 16:21:14 -07:00
Andrew Waterman c22438b822 Fix an overly strict D$ assertion 2016-10-06 15:52:46 -07:00
Andrew Waterman 5980dc160f Don't allow multiple entries for same PC in BTB 
Necessary for RVC forward-progress guarantee.
 2016-10-06 11:30:45 -07:00
Andrew Waterman eddf1679f5 Use <> instead of := for bi-directional connections 2016-10-04 22:29:39 -07:00
Andrew Waterman 4f6eb38eeb Enable Verilator parallel builds 2016-10-04 22:29:39 -07:00
Andrew Waterman 6472d4c245 Print Verilator random seed when +verbose is passed 2016-10-04 22:29:39 -07:00
Andrew Waterman 67593fdf2d Explicitly zap some S-mode CSRs when not using S-mode 2016-10-04 22:29:39 -07:00
Andrew Waterman 968851f7e3 Default to configurable priorities 
up-to-7 levels is kind of arbitrary, but I'm unwilling to introduce
a new Parameter at the moment.
 2016-10-04 22:29:39 -07:00
Andrew Waterman 064c9ebdc6 Don't report I$ fetch faults on TLB misses! 2016-10-04 14:37:25 -07:00
Andrew Waterman 516481b68b Improve back-to-back integer multiplication performance 
More exact hazard checking in the decode stage avoids a pipeline flush.
 2016-10-04 14:37:25 -07:00
Andrew Waterman 7b69f1f261 Don't enter D$ flush state machine if grant outstanding 2016-10-04 14:37:25 -07:00
Andrew Waterman 28beb33943 Make any intervening load/store/fence fail an LR/SC sequence 
This catches LR/SC misuses more quickly.
 2016-10-04 14:37:25 -07:00
Andrew Waterman e0188f8aa4 Don't implicitly fence on CSR instructions 
CSRs that have an effect on I/O should use an explicit FENCE.
 2016-10-01 19:44:10 -07:00
Andrew Waterman b772edcb1b Allow hit-under-MMIO and multiple MMIOs in blocking D$ 
The latter feature is by default disabled, since there aren't enough
ID bits.
 2016-10-01 19:44:05 -07:00
Andrew Waterman e928b741ce Default mtvec=0, not None 
Setting it to None was a mistake.  It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.
 2016-09-29 13:52:41 -07:00
Andrew Waterman 8e63f4a1a5 Remove ClockToSignal and vice-versa 
Clock.asUInt and Bool.asClock now suffice.
 2016-09-21 16:17:14 -07:00
Andrew Waterman 2ab61f1a71 Chisel implicit clock is now named clock, not clk 2016-09-21 16:16:47 -07:00
Andrew Waterman 12d0c00822 Fix mtime RegField handling 
RegField.bytes was unconditionally overwriting mtime, preventing it
from ever ticking.  Avoid RegField.bytes by splitting mtime into
a Seq of words.
 2016-09-20 15:00:52 -07:00
Andrew Waterman 3b38736a8e Make BaseTopModule and BaseTopModule abstract 
They aren't meant to be directly instantiated.
 2016-09-19 17:18:35 -07:00
Andrew Waterman d0572d6aab Allow reset vector to be set dynamically 
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins.  Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.

Additionally, allow MTVEC to *not* be reset.  In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does.  So the reset value is superfluous.
 2016-09-19 17:18:03 -07:00
Andrew Waterman e6c1bcfedd Expose carry-out bits from WideCounter 2016-09-19 15:54:17 -07:00
Andrew Waterman a49814c667 Allow WideCounter to not be reset 2016-09-18 18:45:51 -07:00
Andrew Waterman 86b70c8c59 Rename PRCI to CoreplexLocalInterrupter 
That's all it's doing (there wasn't much PRC).
 2016-09-16 14:26:34 -07:00
Andrew Waterman 6134384da4 Fix deprecation warnings 2016-09-16 14:24:19 -07:00
Andrew Waterman a94b4af92d Simplify AsyncResetRegVec and make AsyncResetReg companion object 2016-09-16 11:25:10 -07:00
Andrew Waterman 565444c40e Make UnitTestCoreplex cope with an external MMIO network 2016-09-14 12:19:21 -07:00
Andrew Waterman 2572cd3f7c Add missing dependency 2016-09-14 11:50:28 -07:00
Andrew Waterman 5828e6042e Work around https://github.com/ucb-bar/firrtl/issues/299 2016-09-14 11:47:10 -07:00
Andrew Waterman c3ddff809b Move PRCI from Coreplex to always-on block, where it belongs 2016-09-14 11:01:05 -07:00
Andrew Waterman 5566bf1b13 Don't route PLIC interrupts through PRCI 
The PLIC is local to the Coreplex, and PRCI should not be.
 2016-09-14 11:01:05 -07:00
Andrew Waterman 38b13da2f4 Bump chisel and firrtl 2016-09-14 11:01:05 -07:00
Andrew Waterman 61cbe6164d Add option to execute JAL from decode stage 
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC.  Caveat emptor.
 2016-09-13 02:32:00 -07:00
Andrew Waterman 88440ebf89 Use PseudoLRU in BTB when possible (for powers of two) 2016-09-12 16:52:03 -07:00
Andrew Waterman 266a2f24bd Disable Mul early out by default if XLen == 32 
With a default unroll of 8, it doesn't help performance, but costs area.
 2016-09-12 16:50:08 -07:00
Andrew Waterman 96185e4b16 tighten an assert condition 
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
 2016-09-12 16:49:46 -07:00
Andrew Waterman beb141a20b Allow M, A, D, C extensions to be disabled in misa register 2016-09-12 16:49:46 -07:00
Andrew Waterman 656aa78f7d Pipeline FMAs more deeply by default 
Rocket's QoR has improved enough that the FMAs are on the critical
path.  This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
 2016-09-09 11:06:42 -07:00
Andrew Waterman eaa4b04ee5 Check D$ store->load collisions more precisely 
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
 2016-09-09 11:06:42 -07:00
Andrew Waterman 02a2439222 Support a degenerate PLIC with no interrupts 
Resolves #249
 2016-09-07 11:21:13 -07:00
Andrew Waterman 70cfd7ce13 Make DefaultRV32Config be RV32IMAFCS, not RV32IMC 
The latter is more the domain of TinyConfig.
 2016-09-07 01:58:25 -07:00
Andrew Waterman a7f47f3c23 Reduce default BTB size 
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a.  The intent was to
fit the dhrystone working set (rofl) which the new value of 40 does.
 2016-09-07 01:51:27 -07:00
Andrew Waterman 9fea4c83da Add RV32F support 2016-09-07 00:05:39 -07:00
Andrew Waterman 66e9f027e0 Add MuxT to mux on Tuple2 and Tuple3 2016-09-07 00:05:38 -07:00
Andrew Waterman 511cc6c5c5 Evaluate arg to Boolean.option lazily 2016-09-07 00:05:38 -07:00
Andrew Waterman a0dcd42e80 avoid erroneously setting tags valid during flush 2016-09-07 00:05:38 -07:00
Andrew Waterman 63679bb019 Add support for L1 data scratchpads instead of caches 
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).

They are currently limited to single cores without DRAM.  We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
 2016-09-02 16:22:07 -07:00
Andrew Waterman fb50f7c9dd Set default TileLink width to XLen 2016-09-02 15:27:54 -07:00
Andrew Waterman e23e4d6de5 Add ClientUncachedTileLinkEnqueuer utility 2016-09-02 15:27:54 -07:00
Andrew Waterman 7aeb42fa55 Allow narrow TL interface on PRCI; make mtime writable 2016-09-02 15:27:54 -07:00
Andrew Waterman c05ba1e864 Add TileId parameter, generalizing GroundTestId 
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
 2016-09-02 00:10:50 -07:00
Andrew Waterman f4524e4c91 Add PML for Boolean.option; use it 2016-08-31 13:43:04 -07:00
Andrew Waterman 2dfcf18167 Filter simv command-line args starting with -cm 
These confuse HTIF, so don't pass them through.

Contributed by @scottj97.
 2016-08-31 13:39:35 -07:00
Andrew Waterman 8dbee2b133 Don't conditionalize running bmarks on UseVM 2016-08-29 13:43:29 -07:00
Andrew Waterman 07d48df88a Get rid of FPU RoCC port logic when RoCC not present 
The previous approach used ex_reg_valid to determine whether to
source data from the FPU or RoCC.  Thus, when the RoCC was not
present, it was still creating muxes.  Using ex_cp_valid instead
gets rid of them.
 2016-08-29 12:59:17 -07:00
Andrew Waterman f91552a650 Add performance counter support 2016-08-29 12:31:52 -07:00
Andrew Waterman 1e3339e97c Update breakpoints to match @timsifive's debug spec 2016-08-29 12:31:52 -07:00
Andrew Waterman 9ca82dd397 reset default MulDiv config to moderately fast default 
Closes #228.

In commit 3f8c60bbd6 I inadvertently
changed the configuration while refactoring it.
 2016-08-29 12:31:52 -07:00
Andrew Waterman 33eaf08b60 set missing port direction 
Ideally, chisel should flag this as an error.
 2016-08-29 12:31:52 -07:00
Andrew WatermanandHoward Mao 114226252b Hierarchicalize D$ config 2016-08-19 12:12:34 -07:00
Andrew WatermanandHoward Mao 3f8c60bbd6 Hierarchicalize FPU and MulDiv parameters 
This gets some leaf-level parameters out of the global parameterization,
better separating concerns.  This commit also allows disabling the
M extension.
 2016-08-19 12:06:17 -07:00
Andrew WatermanandHoward Mao fee5d2b1ea Remove parameters for some things that aren't parameterizable 
Heads up @colinschmidt and @ccelio.  I'm removing these because
they are ISA constants and so are not truly parameters, so the
parameter place is not the place for them.  Since BOOM and Hwacha
both depend on rocket, you should be able to obtain them by
instantiating/extending rocket.HasCoreParameters.
 2016-08-19 12:04:13 -07:00
Andrew Waterman 5164f947c0 Validate mstatus.mpp/dcsr.prv values on MRET/DRET 
The registers can still hold invalid values, but an attempt to switch
to the mode stored therein will instead go to an implemented mode.
 2016-08-17 15:39:34 -07:00
Andrew Waterman ed827678ac Write test harness in Chisel 
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
 2016-08-15 23:27:27 -07:00
Andrew Waterman 2d1d7266f5 Fix RV64 badaddr value on instruction faults with large addresses 
We were relying on ALU passthrough for this, but failed to override the
ALU dw argument, so bits above 31 could be discarded.
 2016-08-15 23:09:09 -07:00
Andrew Waterman 2906c75167 Remove fsim, as it is the same as vsim, modulo CONFIG 2016-08-09 15:42:22 -07:00
Andrew Waterman 1b8f919db2 Remove unused CoreName parameter 2016-08-09 15:24:59 -07:00
Andrew Waterman 458520c8f6 Use a generic UInt for TileLink op sizes, rather than MT_xx enum 2016-08-09 15:24:51 -07:00
Andrew Waterman a857b08c59 [rocket] compute D$ tag bits based upon # of arbiter ports 2016-08-09 14:40:48 -07:00
Andrew Waterman cc0f8962fb [rocket] take physical memory attribute check off critical path 
Cache the attributes in the TLB instead.
 2016-08-02 17:21:03 -07:00
Andrew Waterman 76f33d88a6 [rocket] Respect physical memory protection during page table walks 2016-08-02 17:20:49 -07:00
Andrew Waterman 5d4f6383f2 [rocket] Automatically kill D$ access on address exceptions 
Doing this internally to the cache eliminates a long control path
from the cache to the core and back to the cache.
 2016-08-02 17:20:49 -07:00
Andrew Waterman b54db0ba23 [rocket] don't update BTB on not-taken branches 
Only update the BHT; don't set the target prediction to pc+4.
 2016-08-02 17:20:49 -07:00
Andrew Waterman 64bde1060c [rocket] remove unused code in ibuf 2016-08-02 15:26:09 -07:00
Andrew Waterman 2ce702dc0a [rocket] fix PTW critical path 
Pipeline the killing of a D$ request following a PTW cache hit.
 2016-08-02 15:19:48 -07:00
Andrew Waterman 7e9d139e49 [rocket] remove rocket-specific require() from HasCoreParameters 2016-08-02 15:19:48 -07:00
Andrew Waterman 791a27748b Update firrtl and remove firrtl hack in plic 2016-08-02 15:19:48 -07:00
Andrew Waterman fe670e5421 Stop using deprecated FileSystemUtilities to create files 2016-07-31 18:04:56 -07:00
Andrew Waterman 832e56d3c7 Fix toBits/toUInt/toSInt deprecation warnings 2016-07-31 17:13:52 -07:00
Andrew Waterman a6e009d8de [rocket] Fix frontend mask when fetchWidth == 1 2016-07-31 15:21:17 -07:00
Andrew Waterman c49dad2e9d Improve PTW QoR 2016-07-29 17:56:42 -07:00
Andrew Waterman cc635c386f Make Chisel3 the default version for SBT 2016-07-29 17:56:42 -07:00
Andrew Waterman 058396aefe [rocket] Implement RVC 2016-07-29 17:56:42 -07:00
Andrew Waterman c465120610 [rocket] use more standard pattern for computing integer min 2016-07-29 17:56:42 -07:00
Andrew Waterman ffac86b041 [rocket] only write badaddr on certain exceptions 2016-07-29 17:56:42 -07:00
Andrew Waterman 0d3d9fca25 [rocket] Allow zapping of BTB entries 
This is necessary to guarantee forward progress with RVC, since if the
BTB keeps mispredicting, the processor might never successfully
fetch both halves of a misaligned instruction.
 2016-07-29 17:56:42 -07:00
Andrew Waterman 8e0392f24b [rocket] don't hard-code instruction width in BHT 2016-07-29 17:56:42 -07:00
Andrew Waterman 7cf44f9b25 clean up WideCounter implementation 2016-07-15 00:51:01 -07:00
Andrew Waterman ba08255450 bump rocket 2016-07-14 22:11:19 -07:00
Andrew Waterman d78f1aacd0 Clean up some zero-width wire cases using UInt.extract 2016-07-14 22:08:01 -07:00
Andrew Waterman da512d4230 Explicitly discard BTB index LSBs 2016-07-14 17:10:27 -07:00
Andrew Waterman 768403f8fa Bump rocket; remove ICacheBufferWays parameter 2016-07-14 12:50:16 -07:00