riscv/rocket-chip
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Work around https://github.com/ucb-bar/firrtl/issues/299

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This commit is contained in:
Andrew Waterman 2016-09-14 11:47:10 -07:00
parent c3ddff809b
commit 5828e6042e
1 changed files with 2 additions and 4 deletions
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6
src/main/scala/junctions/hasti.scala
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@ -521,10 +521,8 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
// In case we are stalled, we need to hold the read data
val d_rdata = holdUnless(mem.read(a_address, read), RegNext(read))
// Whenever the port is not needed for reading, execute pending writes
when (!read) {
when (p_valid) { mem.write(p_address, p_wdata, p_mask.toBools) }
p_valid := Bool(false)
}
when (!read && p_valid) { mem.write(p_address, p_wdata, p_mask.toBools) }
when (!read) { p_valid := Bool(false) }
// Record the request for later?
when (ready && a_request && a_write) {