riscv/rocket-chip
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Disable Mul early out by default if XLen == 32

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With a default unroll of 8, it doesn't help performance, but costs area.
This commit is contained in:
Andrew Waterman 2016-09-12 16:50:08 -07:00
parent 96185e4b16
commit 266a2f24bd
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/Configs.scala
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@ -125,7 +125,7 @@ class BaseCoreplexConfig extends Config (
case FastLoadByte => false
case XLen => 64
case FPUKey => Some(FPUConfig())
case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = true, divEarlyOut = true))
case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true))
case UseAtomics => true
case UseCompressed => true
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))