Andrew Waterman
a6a88fce19
Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
...
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
2013-05-01 16:34:45 -07:00
Andrew Waterman
63a38e7982
Revert "temp"
...
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
2013-05-01 16:34:33 -07:00
Henry Cook
b6945408cb
temp
2013-05-01 10:24:36 -07:00
Henry Cook
722bc917d3
broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle
2013-05-01 10:05:54 -07:00
Andrew Waterman
1501e90c1f
interlock probe unit on tag RAW hazards
2013-04-30 00:38:22 -07:00
Henry Cook
e8b20f3d38
clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant
2013-04-25 17:41:04 -07:00
Andrew Waterman
50ccc20bf3
replace RDNPC with AUIPC
2013-04-22 04:20:15 -07:00
Henry Cook
db5a060c7d
fix io dir
2013-04-10 13:47:30 -07:00
Andrew Waterman
ae7720e284
guarantee LR/SC forward progress
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the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
2013-04-07 19:27:21 -07:00
Andrew Waterman
e74e032c87
simplify MSHR memory response logic
2013-04-06 01:03:37 -07:00
Andrew Waterman
1abb9277db
fix LR/SC atomicity violation
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note, it's still not starvation-free.
2013-04-05 19:13:38 -07:00
Andrew Waterman
8cbdeb2abf
add LR/SC support
2013-04-04 17:07:09 -07:00
Andrew Waterman
fc46daecf6
don't flush pipeline on writes to side-effect-free PCRs
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notably, K0, K1, and EPC
2013-04-04 17:07:09 -07:00
Andrew Waterman
8b439ef20d
only support setpcr/clearpcr of SR
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the full PCR RMW support was wasted area/power
2013-04-04 17:07:08 -07:00
Andrew Waterman
d43f484feb
take interrupts on nonzero fromhost values
2013-04-04 17:07:08 -07:00
Andrew Waterman
d4a3351cfc
expose pending interrupts in status register
2013-04-04 17:07:08 -07:00
Henry Cook
f8aebcbf8c
fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
2013-04-04 15:50:29 -07:00
Henry Cook
16113a96ba
fixes after merge
2013-03-25 19:09:08 -07:00
Henry Cook
95f0a688e9
Merge branch 'release-xacts'
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Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
2013-03-20 17:37:50 -07:00
Henry Cook
273bd34091
Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
2013-03-20 15:53:36 -07:00
Henry Cook
6d2541aced
nTiles -> nClients in LogicalNetworkConfig
2013-03-20 14:12:36 -07:00
Andrew Waterman
ea9d0b771e
remove aborts; simplify probes
2013-03-19 15:29:40 -07:00
Yunsup Lee
0f50970913
move HellaQueue to uncore
2013-03-19 00:43:20 -07:00
Henry Cook
e0361840bd
writebacks on release network pass asm tests and bmarks
2013-02-28 18:11:40 -08:00
Andrew Waterman
35349d227f
update to new Mem style
2013-02-20 16:09:46 -08:00
Andrew Waterman
9f89c812b7
fix HTIF memory size reporting
2013-01-29 23:08:25 -08:00
Yunsup Lee
a0bd0adeb2
change write/read port ordering for vlsi_mem_gen script
2013-01-29 21:32:42 -08:00
Andrew Waterman
66eb3720a4
fix SRAM semantics bug in HellaFlowQueue
2013-01-29 21:16:42 -08:00
Yunsup Lee
60bd3a6413
Revert "shuffled FPU control logic around to make functional unit retiming work better"
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This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
2013-01-29 19:34:55 -08:00
Andrew Waterman
6275e009f8
fix HellaQueue deq.valid signal
2013-01-28 20:57:43 -08:00
Andrew Waterman
45d8066f45
add HellaQueue, an SRAM-based queue
2013-01-28 20:54:25 -08:00
Andrew Waterman
37c67f1d87
pipeline reset to the vector unit
2013-01-28 17:56:32 -08:00
Rimas Avizienis
f2df6147df
shuffled FPU control logic around to make functional unit retiming work better
2013-01-28 17:17:09 -08:00
Henry Cook
f5729c9f25
removed ack_required field from grant messages
2013-01-28 16:44:17 -08:00
Henry Cook
8cbd316b5e
Merge branch 'ready-sig-fix' into pin-cleanup
2013-01-27 23:04:58 -08:00
Henry Cook
931cffa749
ready signal fix
2013-01-27 23:04:35 -08:00
Henry Cook
83c207c852
pin cleanup in htif
2013-01-27 12:00:28 -08:00
Henry Cook
409b549d3c
actually cleared up tile ios
2013-01-27 11:27:09 -08:00
Henry Cook
696dd102eb
cleans up unconnected tile io pins (networking headers overwritten at top level)
2013-01-27 10:59:41 -08:00
Andrew Waterman
c890099e09
add System Control Register space to HTIF
2013-01-24 23:41:24 -08:00
Andrew Waterman
575bd3445a
re-generalize scoreboard
2013-01-24 18:00:39 -08:00
Andrew Waterman
1fbc20450e
don't allow simultaneous reads and writes to the tag ram
2013-01-24 17:55:00 -08:00
Andrew Waterman
37ee843b2c
don't use reset combinationally
2013-01-24 17:55:00 -08:00
Andrew Waterman
bb6fbddf1f
don't probe the mshr file to inquire about refills
2013-01-24 17:54:59 -08:00
Andrew Waterman
5b9f938263
correctly sign-extend badvaddr, epc, and ebase
2013-01-24 17:54:59 -08:00
Rimas Avizienis
63060bc0a8
minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
2013-01-23 19:27:53 -08:00
Henry Cook
6b00e7ff74
New TileLink bundle names
2013-01-21 17:18:23 -08:00
Henry Cook
a2fa3fd04d
Refactored packet headers/payloads
2013-01-15 15:50:37 -08:00
Henry Cook
e1225c5114
standardize IO naming convention
2013-01-07 13:41:36 -08:00
Henry Cook
261e14f831
Refactored uncore conf
2013-01-07 13:41:36 -08:00
Andrew Waterman
78868f6075
add config option to trade mul/div area for speed
2013-01-06 03:47:17 -08:00
Andrew Waterman
ce9f4881d2
remove broken multiplier early out
2013-01-06 03:47:00 -08:00
Andrew Waterman
05f19b21d0
merge multiplier and divider
2012-12-12 02:22:47 -08:00
Andrew Waterman
c921fc34a9
merge ALU left and right shifters
2012-12-12 02:22:34 -08:00
Andrew Waterman
f5c53ce35d
add ecc support to d$ data rams
...
i haven't injected errors yet; it may well be incorrect.
2012-12-11 15:58:53 -08:00
Andrew Waterman
3f59e439ef
fix d$ tag raw hazard
2012-12-07 15:14:20 -08:00
Andrew Waterman
e9752f1d72
pipeline host pcr access
2012-12-06 14:22:07 -08:00
Andrew Waterman
4dda38204f
fix d$ reset bug
2012-12-06 03:13:22 -08:00
Andrew Waterman
290d3d226c
fix AMO and store bypass bugs
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thanks, torture tester
2012-12-06 02:07:52 -08:00
Andrew Waterman
4608660f6e
torture revealed a couple bugs
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FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
2012-12-04 05:57:53 -08:00
Andrew Waterman
90cae54ac4
fix D$ read/write concurrency bug
2012-11-27 02:42:27 -08:00
Andrew Waterman
9c857b83f0
refactor PCR file
2012-11-27 01:28:06 -08:00
Andrew Waterman
64674d4d39
clean up PTW and support PADDR_BITS < VADDR_BITS
2012-11-26 20:38:45 -08:00
Andrew Waterman
608f65e716
don't wastefully read 2x the bits from D$ RAMs
2012-11-26 20:34:30 -08:00
Andrew Waterman
352bb464b5
clock gate X/M and M/W store data registers
2012-11-26 20:33:41 -08:00
Andrew Waterman
8a6ff5f9aa
fix D$ writeback bug
...
I swear I did this last week... perhaps I am finally losing it!
2012-11-25 19:46:48 -08:00
Andrew Waterman
de2f28193a
get rid of more global constants
2012-11-25 04:24:25 -08:00
Andrew Waterman
c036cdc1ea
add option for 2-cycle load-use delay
2012-11-24 22:01:08 -08:00
Andrew Waterman
b514c7b725
clean up I$ parity code
2012-11-24 22:00:43 -08:00
Andrew Waterman
55082e45c4
add AVec, which automatically infers element type
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should consider modifying Vec as such
2012-11-24 18:19:28 -08:00
Andrew Waterman
2b26082132
use 1r1w ram for tags; merge tags & permissions
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setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
2012-11-20 04:09:26 -08:00
Andrew Waterman
72f94d1141
fix virtual address sign extension detection
2012-11-20 04:06:57 -08:00
Andrew Waterman
30038bda8a
bypass stores to subsequent loads
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since we handle subword stores as RMW operations, this occurs frequently
2012-11-20 01:33:32 -08:00
Yunsup Lee
395e4e3dd6
andrew'x fix for D$ corner case in writeback->abort->probe
2012-11-18 03:11:06 -08:00
Yunsup Lee
06eeb90e2a
vector unit interfaces to the new D$
2012-11-17 20:07:41 -08:00
Yunsup Lee
81d711e892
fix D$ bug; now D$ doesn't respond to prefetches
2012-11-17 20:06:13 -08:00
Andrew Waterman
29bc361d6c
remove global constants; disentangle hwacha a bit
2012-11-17 17:24:08 -08:00
Andrew Waterman
5a7777fe4d
clock gate integer datapath more aggressively
2012-11-17 06:48:44 -08:00
Andrew Waterman
cc067026a2
pipeline D$ response -> FPU regfile
2012-11-17 06:48:11 -08:00
Andrew Waterman
e68b039133
fix misc. D$ control bugs
2012-11-17 06:47:27 -08:00
Andrew Waterman
dad7b71062
provide cmd/addr with cache response
2012-11-16 21:26:12 -08:00
Andrew Waterman
cb8ac73045
provide store data with cache response
2012-11-16 21:15:13 -08:00
Andrew Waterman
9e010beffe
fix D$ refill bug
2012-11-16 21:05:29 -08:00
Andrew Waterman
8dce89703a
new D$ with better QoR and AMO pipelining
...
Vector unit is disabled because nack handling needs to be fixed.
2012-11-16 02:39:33 -08:00
Andrew Waterman
a90a1790a5
improve tlb qor
2012-11-16 01:59:38 -08:00
Andrew Waterman
ff8c736d94
move icache invalidate out of request bundle
2012-11-16 01:55:45 -08:00
Andrew Waterman
6d10115b19
fix D$ tag width
2012-11-15 16:46:39 -08:00
Yunsup Lee
be1980dd2d
refactored vector queue interface
2012-11-07 01:15:33 -08:00
Yunsup Lee
8764fe786a
refactored vector tlb
2012-11-06 23:53:52 -08:00
Yunsup Lee
9a02298f6f
andrew's fix for tlb lockup
2012-11-06 23:52:58 -08:00
Andrew Waterman
4d1ca8ba3a
remove more global consts; refactor DTLBs
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D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
2012-11-06 08:13:44 -08:00
Andrew Waterman
e76892f758
remove more global constants
2012-11-06 02:55:45 -08:00
Andrew Waterman
c5b93798fb
factor out more global constants
2012-11-05 23:52:32 -08:00
Yunsup Lee
ee081d1671
modify code to fix UFix := Bits error
2012-11-05 01:35:55 -08:00
Yunsup Lee
2a25307a8f
revamp the vector unit with the new frontend
2012-11-05 01:35:55 -08:00
Andrew Waterman
5b20ed71be
move rd=0 check into bypass logic
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before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
2012-11-05 01:30:57 -08:00
Andrew Waterman
5e103054fd
fix bug in quine mccluskey
2012-11-05 00:28:25 -08:00
Andrew Waterman
e9eca6a95d
refactor I$ config; remove Top class
2012-11-04 16:59:36 -08:00
Andrew Waterman
7380c9fe60
aggressively clock gate int and fp datapaths
2012-11-04 16:40:14 -08:00
Andrew Waterman
bd2d61de03
use 8T SRAM for I$; gate clock more aggressively
2012-11-04 16:39:25 -08:00
Andrew Waterman
fedee6c67d
add generic error correcting codes
2012-10-30 01:03:47 -07:00
Andrew Waterman
5773cbb68a
rejigger htif to use UncoreConfiguration
2012-10-18 17:26:03 -07:00
Henry Cook
e2eb7ce8e9
Cleanup git incompetence
2012-10-16 16:54:58 -07:00
Henry Cook
88ac5af181
Merged consts-as-traits
2012-10-16 16:32:35 -07:00
Henry Cook
6cff1c13d8
Refer to traits moved to uncore, add UncoreConfiguration to top
2012-10-16 14:22:23 -07:00
Andrew Waterman
b9a2af697d
turn off HAVE_VEC as it's currently broken
...
the new I$/frontend needs to be integrated
2012-10-16 07:38:19 -07:00
Andrew Waterman
0a640f2cc6
make DecodeLogic deterministic (hopefully)
2012-10-16 04:51:21 -07:00
Andrew Waterman
5821900329
don't refetch from I$ if on same 16B block
2012-10-16 02:24:38 -07:00
Andrew Waterman
b955985b38
improve divider QoR
2012-10-16 02:24:38 -07:00
Andrew Waterman
197154c485
use BTB for JALR
2012-10-16 02:24:37 -07:00
Andrew Waterman
fc648d13a1
remove old Mux1H; add implicit conversions
2012-10-16 02:24:37 -07:00
Andrew Waterman
661f8e635b
merge I$, ITLB, BTB into Frontend
2012-10-16 02:24:37 -07:00
Andrew Waterman
fcd69dba98
add optional early-out to mul/div
2012-10-16 02:24:37 -07:00
Andrew Waterman
27ddff1adb
simplify and improve multiplier
2012-10-16 02:24:37 -07:00
Henry Cook
8970b635b2
improvements to implicit RocketConfiguration parameter
2012-10-15 16:29:49 -07:00
Henry Cook
a7a4e65690
Initial verison of reading config from files
2012-10-15 16:05:50 -07:00
Henry Cook
5d2a470215
all rocket-specific arbiters in one file and refactored traits slightly
2012-10-15 16:05:32 -07:00
Huy Vo
1864e41361
memserdes + slowio out of rocket and into uncore
2012-10-10 15:25:24 -07:00
Huy Vo
fe21142972
fixed memdessert unpacking
2012-10-09 13:03:17 -07:00
Henry Cook
9025d0610c
first pass at configuration object passed as implicit parameter
2012-10-07 22:37:29 -07:00
Henry Cook
dfdfddebe8
constants as traits
2012-10-07 22:20:03 -07:00
Henry Cook
b5ff436092
decode constant object split into multiple objects
2012-10-05 15:50:42 -07:00
Andrew Waterman
ed8cc4a1cf
eliminate D$ probe->WB critical path
2012-10-04 09:05:14 -07:00
Huy Vo
e909093f37
factoring out uncore into separate uncore repo
2012-10-01 16:08:41 -07:00
Henry Cook
b9a9664de5
uncore and rocket changes for new xact types
2012-10-01 10:47:36 -07:00
Huy Vo
d9cb96c0ae
factored out common stuff to ChiselUtil
2012-09-27 22:53:34 -07:00
Andrew Waterman
667b4ee858
remove Queue flush port (override reset instead)
2012-08-22 13:39:19 -07:00
Andrew Waterman
d4a001b867
add PriorityMux; use to implement PriorityEncoder
2012-08-22 13:38:25 -07:00
Andrew Waterman
743e032f06
generalize interface to DecodeLogic
2012-08-22 13:38:07 -07:00
Andrew Waterman
0f20771664
rename queue to Queue
...
fixes build with case-insensitive file system
2012-08-08 22:11:59 -07:00
Andrew Waterman
897a4e349b
fix some LLC control bugs
2012-08-06 17:10:04 -07:00
Andrew Waterman
e9c35b4923
ameliorate DTLB kill->rdy critical path
2012-08-06 17:05:05 -07:00
Andrew Waterman
b94e6915ab
refactor IPIs; use new tohost/fromhost protocol
2012-08-03 19:00:34 -07:00
Andrew Waterman
6510f020c7
fix deadlock in coherence hub
2012-08-03 19:00:03 -07:00
Andrew Waterman
e3726c4db0
fix control bug in LLC
...
structural hazard on tag ram caused deadlock
2012-08-03 18:59:37 -07:00
Andrew Waterman
def913096e
pipeline LLC further
2012-07-31 17:45:14 -07:00
Andrew Waterman
3a8f3e0de5
further pipeline the LLC
2012-07-30 20:12:11 -07:00
Andrew Waterman
80c243469e
add flow queues and skid buffers
...
hopefully they work
2012-07-30 18:47:12 -07:00
Andrew Waterman
be4fa936dd
fix PriorityEncoderOH bug
2012-07-30 18:28:54 -07:00
Andrew Waterman
2ec76390e3
improve PriorityEncoderOH and add Counter util
2012-07-30 16:06:55 -07:00
Yunsup Lee
2af84f994a
remove reset pin on llc
2012-07-28 21:14:51 -07:00
Yunsup Lee
0a1cd1175c
add reset pin to llc
2012-07-27 18:44:39 -07:00
Huy Vo
db91c4cf6c
hwacha
2012-07-27 18:13:20 -07:00
Huy Vo
32a16d183f
consts file doesn't depend on WIDTH_PVFB if HAVE_PVFB == false
2012-07-27 18:13:20 -07:00
Andrew Waterman
130fa95ed6
expand HTIF's PCR register space
2012-07-27 14:52:39 -07:00
Andrew Waterman
7778802395
reduce number of outstanding transactions
2012-07-26 14:51:41 -07:00
Andrew Waterman
9c50621a19
remove chip-specific uncore gunk
2012-07-26 03:26:52 -07:00
Andrew Waterman
a5bea4364f
memory system bug fixes
2012-07-26 00:05:21 -07:00
Yunsup Lee
3a2b305ddf
change htif width to 16
2012-07-25 17:25:50 -07:00
Andrew Waterman
177dbdadd9
merge HTIF port and backup memory port
2012-07-25 00:18:02 -07:00
Yunsup Lee
309193dd07
change llc size
2012-07-24 14:10:29 -07:00
Yunsup Lee
6541cf22a4
fix bug in coherence hub, respect xact_rep.ready
2012-07-23 20:56:55 -07:00
Yunsup Lee
f4e3e72ad1
hoist HTIF_WIDTH out to consts
2012-07-23 17:30:04 -07:00
Andrew Waterman
a21c355114
fix htif split request/response
2012-07-23 17:15:16 -07:00
Andrew Waterman
938effc053
don't dequeue probe queue during reset
2012-07-22 21:05:52 -07:00
Yunsup Lee
379f021359
change ioHTIF interface between the tile/uncore boundary to cope with asynchrony
2012-07-22 18:26:02 -07:00
Yunsup Lee
c892950bf1
hoist out uncore as its own component
2012-07-22 17:48:17 -07:00
Huy Vo
0a97d6ab4d
type casting
2012-07-18 13:03:35 -07:00
Andrew Waterman
f42c6afed2
decouple all interfaces between tile and top
...
also, add an "incoherent" bit to tilelink to indicate no probes needed
2012-07-17 22:55:40 -07:00
Andrew Waterman
4e44ed7400
allow back pressure on IPI requests
2012-07-17 22:55:40 -07:00
Yunsup Lee
f633a55722
fix dcache tag array size
2012-07-16 22:19:03 -07:00
Andrew Waterman
e496cd7584
use Mem to implement queues to speed things up
2012-07-13 21:48:05 -07:00
Huy Vo
fd95159837
INPUT/OUTPUT orderring swapped
2012-07-12 18:16:57 -07:00
Andrew Waterman
bac82762d3
use only one (wide) tag ram for set assoc. caches
2012-07-12 14:50:12 -07:00
Andrew Waterman
429fcbed8e
fix some LLC bugs
2012-07-11 17:56:39 -07:00
Andrew Waterman
f645fb4dd7
add L2$
...
It still has performance bugs but no correctness bugs AFAIK.
2012-07-10 05:23:29 -07:00
Andrew Waterman
5035374f36
update to new chisel
2012-07-08 17:59:41 -07:00
Andrew Waterman
39d198ecdc
fix htif handling of large memory reads
2012-06-26 19:12:11 -07:00
Andrew Waterman
4e5f874266
update to new chisel/hwacha
2012-06-08 00:13:14 -07:00
Huy Vo
a99cebb483
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
2012-06-06 18:22:56 -07:00
Huy Vo
04304fe788
moving util out into Chisel standard library
2012-06-06 12:51:26 -07:00
Huy Vo
c975c21e44
views removed
2012-06-06 12:51:26 -07:00
Andrew Waterman
943b6d0616
remove debug println
2012-06-06 02:48:48 -07:00
Andrew Waterman
7f6319047e
update to new scala/chisel/Mem
2012-06-06 02:47:22 -07:00
Huy Vo
7408c9ab69
removing wires
2012-05-24 10:42:39 -07:00
Huy Vo
181b20d69c
working vec unit with pvfb
2012-05-24 10:38:14 -07:00
Andrew Waterman
faee45bf4c
fix setpcr/clearpcr not writing rd
2012-05-21 07:25:35 -07:00
Yunsup Lee
c9602a0d2e
fix vector control decode bug
2012-05-15 10:26:37 -07:00
Gage W Eads
d0bc995c88
Fixed IRQ_IPI -> IRQ_TIMER typo
2012-05-14 22:25:12 -07:00
Andrew Waterman
a2f6d01c1b
add programmable coreid register
2012-05-09 03:09:22 -07:00
Andrew Waterman
e0e1cd5d32
add IPIs and an IPI test
...
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
2012-05-08 22:58:00 -07:00
Henry Cook
87cbae2c8a
Removed defunct ioDmem
2012-05-07 17:31:39 -07:00
Andrew Waterman
b851f1b34c
support maximum-MTU HTIF packets
2012-05-03 21:11:43 -07:00
Andrew Waterman
171c87002e
reduce HTIF clock divider for now
2012-05-03 04:21:11 -07:00
Andrew Waterman
e1f9dc2c1f
generalize page table walker
...
also, don't instantiate vitlb when !HAVE_VEC
2012-05-03 02:29:09 -07:00
Andrew Waterman
2d4e5d3813
fix pseudo-LRU verilog generation bug
2012-05-02 19:31:31 -07:00
Henry Cook
622a801bb1
Refactored cpu/cache interface to use nested bundles
2012-05-02 11:54:28 -07:00
Andrew Waterman
65ff397122
improved instruction decoding
...
it now makes use of don't-cares by performing logic minimization
2012-05-01 20:16:36 -07:00
Andrew Waterman
4cfa6cd9a8
force Top.main's return type to Unit
2012-05-01 19:55:16 -07:00
Andrew Waterman
5819beed64
use parameterized FP units
2012-05-01 01:25:43 -07:00
Andrew Waterman
eafdffe125
simplify page table walker; speed up emulator
2012-05-01 01:24:36 -07:00
Andrew Waterman
c13d3e6f88
fix probe tag read-modify-write atomicity violation
2012-04-26 02:29:31 -07:00
Andrew Waterman
66f86a2194
use pseudo-LRU replacement for TLBs
2012-04-26 02:29:30 -07:00
Andrew Waterman
a0378c5d2f
remove faulting TLB entry after page fault
...
this vastly reduces the frequency with which the TLB must be flushed
2012-04-26 02:29:30 -07:00
Andrew Waterman
6d8fc74378
fix DTLB permissions bug
2012-04-26 02:29:30 -07:00
Henry Cook
1ed89f1cab
Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
2012-04-24 17:17:42 -07:00
Henry Cook
55e86b5cf4
Fixed coherence bug: probe counting for single tile
2012-04-24 17:17:13 -07:00
Henry Cook
a39080d0b1
Fixed abort bug: xact_abort.ready was not pinned high
2012-04-24 17:16:40 -07:00
Andrew Waterman
fb4408b150
fix AMO replay/coherence deadlock
2012-04-15 22:56:02 -07:00
Andrew Waterman
724735f13f
fix writeback bug
2012-04-13 03:16:48 -07:00
Andrew Waterman
00d934cfac
fix coherence bugs in cache
2012-04-12 21:57:37 -07:00
Henry Cook
fef58f1b3a
Policy determined by constants. MSI policy added.
2012-04-11 17:56:59 -07:00
Andrew Waterman
c0ec3794bf
coherence mostly works now
2012-04-10 02:22:45 -07:00
Henry Cook
3cdd166153
Refactored coherence as member rather than trait. MI and MEI protocols.
2012-04-10 00:09:58 -07:00
Henry Cook
9c8f849f50
defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy
2012-04-09 23:29:32 -07:00
Henry Cook
551e09c9d5
changed coherence type width names to represent max sizes for all protocols
2012-04-09 23:29:32 -07:00
Henry Cook
0b4937f70f
changed coherence message type names
2012-04-09 23:29:31 -07:00
Henry Cook
ed79ec98f7
Refactored coherence better from uncore hub, better coherence function names
2012-04-09 23:29:31 -07:00
Andrew Waterman
aee9378712
fix coherence bug with multiple probe replies
2012-04-09 21:40:35 -07:00
Huy Vo
c9c3bd02bc
kill mem stage if fpu nacks in mem stage
2012-04-01 17:02:32 -07:00
Andrew Waterman
7f254d9670
refine FP bugfixes
2012-04-01 14:52:33 -07:00
Huy Vo
c7c35322c2
two bug fixes to fpu
2012-03-31 22:23:51 -07:00
Andrew Waterman
a09e8d1c55
remove I$ prefetcher for now
...
there's a bug in it, and I don't have time to fix it at the moment.
2012-03-27 15:43:56 -07:00
Andrew Waterman
452876af37
fence on vvcfg; implement fence.v.g correctly
2012-03-27 14:49:00 -07:00
Yunsup Lee
bb704dc0c9
fix vector length calc bug, thanks chris and andrew
2012-03-27 12:04:07 -07:00
Andrew Waterman
6bda8674bd
no dessert tonight :(
2012-03-26 23:50:09 -07:00
Yunsup Lee
a70f0414fa
fix a workaroundable bug
2012-03-26 20:51:54 -07:00
Yunsup Lee
32d95e9594
fix -1:0 index problem for direct map case
2012-03-26 17:00:01 -07:00
Andrew Waterman
e2fe525fb6
remove bug from dessert
2012-03-26 14:18:57 -07:00
Yunsup Lee
e6b0e565de
turn HAVE_VEC on
2012-03-26 01:21:39 -07:00
Andrew Waterman
5f53cd4ac1
reduce HTIF width
2012-03-25 23:49:59 -07:00
Andrew Waterman
ef505de017
reduce HTIF width
2012-03-25 23:49:45 -07:00
Andrew Waterman
31f0b600fd
add dessert
2012-03-25 23:03:20 -07:00
Andrew Waterman
1666d3fbd7
loop host.in to host.out during reset
2012-03-25 21:45:10 -07:00
Andrew Waterman
f62a02ab54
remove dumb stuff in top.scala
2012-03-25 21:30:01 -07:00
Andrew Waterman
88bf8a4f23
add mem serdes unit
2012-03-25 17:03:58 -07:00
Andrew Waterman
7fa93da4f5
add backup memory port (disabled for now)
2012-03-25 15:49:32 -07:00
Yunsup Lee
1f33f6bb58
HAVE_VEC is on
2012-03-24 20:54:43 -07:00
Andrew Waterman
86d56ff67b
refactor cpu/i$/d$ into Tile (rather than Top)
2012-03-24 16:57:28 -07:00
Andrew Waterman
3a487ac89b
improve htif<->pcr interface
2012-03-24 16:57:28 -07:00
Andrew Waterman
54fa6f660d
new supervisor mode
2012-03-24 13:03:31 -07:00
Yunsup Lee
65929a62e3
fix reset value for appvl
2012-03-22 15:32:04 -07:00
Yunsup Lee
aaed0241af
get rid of vxcptwait
2012-03-21 15:09:04 -07:00
Yunsup Lee
023734175d
now fence stalls in decode
2012-03-20 17:10:05 -07:00
Yunsup Lee
e450e3aa40
fix irt counter bug regarding vector stuff
2012-03-20 17:09:54 -07:00
Yunsup Lee
7d7d7f49f9
change the tlb arbiter to a round robing one
2012-03-20 15:21:36 -07:00
Yunsup Lee
1cddd5de56
fix amo locking up problem
2012-03-20 02:16:28 -07:00
Yunsup Lee
56cb9b7a63
fix bug in coherence hub, specifically in abort handling logic
2012-03-20 02:16:28 -07:00
Yunsup Lee
c036fff79c
fix id interrupt signal
2012-03-19 15:13:57 -07:00
Yunsup Lee
0edea00166
now HAVE_VEC is true, since it passes the emulator
2012-03-19 03:10:00 -07:00
Yunsup Lee
264732556f
fixes to match verilog X semantics
2012-03-19 03:10:00 -07:00
Andrew Waterman
bd27d0fab2
can now take interrupts on stalled instructions
2012-03-19 01:02:06 -07:00
Andrew Waterman
2ed0be65f9
fix RRArbiter
2012-03-19 00:19:33 -07:00
Yunsup Lee
ba06cd953e
add chosen
2012-03-18 20:43:17 -07:00
Andrew Waterman
c4a91303fb
update vector fence names and encoding
2012-03-18 20:42:38 -07:00
Yunsup Lee
2a01f558ba
fix unmasked valid bug in ctrl_vec
2012-03-18 19:55:24 -07:00
Yunsup Lee
98e10ddc3c
update vector exception instructions
2012-03-18 16:36:12 -07:00
Yunsup Lee
7493d55d3f
add pf fault handling
2012-03-18 15:06:39 -07:00
Yunsup Lee
62ada5ea9e
hookup vitlb ptw port
2012-03-17 23:01:06 -07:00
Yunsup Lee
b793d63182
no vector interrupt masking
2012-03-17 23:01:06 -07:00
Yunsup Lee
8a4f95e617
changes to xcpt handling
2012-03-17 17:50:37 -07:00
Yunsup Lee
8c50c81b81
drop vec_irq_aux pcr register, now everything goes through badvaddr
2012-03-17 14:03:57 -07:00
Yunsup Lee
3b4680a834
add vitlb exception port
2012-03-17 14:03:33 -07:00
Andrew Waterman
a47eeb9571
retime D$ bypass into beginning of EX stage
2012-03-16 18:35:54 -07:00
Andrew Waterman
6c26921766
reduce D$ critical path through page table walker
...
costs an extra cycle per page table level to resolve a TLB miss. too bad.
2012-03-16 18:35:54 -07:00
Yunsup Lee
d38603a4ee
change number of tlb entries
2012-03-16 17:08:03 -07:00
Andrew Waterman
f0157b9e2a
fix coherence bug
...
popping wrong store dependence queue
2012-03-16 01:24:07 -07:00
Andrew Waterman
cfca2d1411
clean up cache interfaces; avoid reserved keywords
2012-03-16 00:44:16 -07:00
Andrew Waterman
820884c7e6
fix probes for smaller cache sizes
...
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
2012-03-15 23:08:30 -07:00
Andrew Waterman
4684171ac6
fix fence.i for associative caches
2012-03-15 21:23:21 -07:00
Andrew Waterman
2b0bc8df2b
use divided clk for htif. UDPATE YOUR FESVR
...
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
2012-03-15 18:36:51 -07:00
Yunsup Lee
ba566f246e
change icache parameters
2012-03-15 15:35:12 -07:00
Yunsup Lee
72006160dc
fix vxcptwait inst bug, it was incorrect when exception_valid was on before do_xcptwait
2012-03-15 02:10:21 -07:00
Yunsup Lee
f972977da1
refactored VMU, now uses one skid buffer
2012-03-15 01:10:17 -07:00
Henry Cook
b5fa86e844
4-way associative by default
2012-03-14 17:51:12 -07:00
Andrew Waterman
7dde7099d2
use broadcast hub and coherent HTIF
2012-03-14 16:44:35 -07:00
Yunsup Lee
b19d783fbd
add vector irq handler
2012-03-14 14:15:28 -07:00
Yunsup Lee
040d62f372
refactored vector exception handling interface
2012-03-13 23:45:34 -07:00
Yunsup Lee
b100544b25
datapath to read out vector state
2012-03-13 23:45:34 -07:00
Yunsup Lee
5655dbd5da
add vvcfg and vtcfg instructions
2012-03-13 23:45:34 -07:00
Andrew Waterman
ab6c9350db
fix minor coherence bugs
2012-03-13 19:10:54 -07:00
Andrew Waterman
1788c34113
parameterize broadcast hub by # of tiles
2012-03-13 17:12:01 -07:00
Andrew Waterman
1492457df5
add probe replies to HTIF
2012-03-13 16:56:47 -07:00
Andrew Waterman
b0f798962c
add probe unit
2012-03-13 16:43:51 -07:00
Huy Vo
fdffb124e3
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-03-13 12:34:39 -07:00
Huy Vo
6fd1527476
fix to rocket vec_dpath, updating makefiles to run xcpt test cases
2012-03-13 12:34:02 -07:00
Henry Cook
287bc1c262
Further refinement of tag_match/tag_hit signals
2012-03-13 11:48:12 -07:00
Andrew Waterman
d76b05bde1
fix way selection on D$ write upgrades
2012-03-13 02:21:02 -07:00
Andrew Waterman
fd29e00db0
support non-power-of-2 queue sizes
...
need to manually wrap queue pointers.
2012-03-13 01:58:28 -07:00
Henry Cook
cbf7b13341
fix hit logic for amos
2012-03-12 22:01:52 -07:00
Henry Cook
6229a33dc4
fixed cache controller flush unit deadlock
2012-03-12 22:01:52 -07:00
Henry Cook
ea0775643b
fixed abort bug
2012-03-12 22:01:52 -07:00
Yunsup Lee
1ba5e7b865
changes to the vector exception interface
2012-03-11 21:38:47 -07:00
Yunsup Lee
113a94a21d
add vector hold waits
2012-03-11 16:29:19 -07:00
Yunsup Lee
e42a4c767e
don't stall on vector fences, keep replaying
2012-03-11 16:29:19 -07:00
Henry Cook
c5dd37ae80
bugfix in locking arbiter
2012-03-11 15:47:27 -07:00
Henry Cook
4ebf637642
More broadcast hub bugfixes
2012-03-11 14:17:27 -07:00
Henry Cook
a4d0025187
fix icache prefetch global_xact_id bug
2012-03-11 00:50:11 -08:00
Yunsup Lee
1aa4b0e93d
going back to null coherence hub
2012-03-10 20:16:20 -08:00
Andrew Waterman
8ffdac9526
fix D$ store-upgrade bug
...
loads to the same address as stores that cause an upgrade
could return the old value
2012-03-10 15:50:10 -08:00
Andrew Waterman
4f4b990a4f
fix null hub store ack bug
2012-03-10 15:19:12 -08:00
Yunsup Lee
44ff22a26f
vector exception handler now handles prefetches correctly
2012-03-10 12:54:36 -08:00
Andrew Waterman
7eb73c325e
fix signedness of zero fmul results
...
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0. Now we
add -0.0 if rs1*rs2 is negative.
2012-03-10 00:21:51 -08:00
Andrew Waterman
e3a68848e0
fix D$ critical paths and fix verilog build
2012-03-09 20:02:51 -08:00
Henry Cook
e591d83e91
Fixed global_xact_id propagation bug
2012-03-09 11:05:44 -08:00
Henry Cook
9319130483
Special cased NTILES == 1 due to log2up revision
2012-03-09 11:04:58 -08:00
Andrew Waterman
85504f0ddc
fix bug in fence.i and improve test
2012-03-09 03:26:05 -08:00
Andrew Waterman
766bac88f8
refactor D$ writebacks and flushes
...
MSHRs now arbitrate for writebacks and handle flushes.
2012-03-09 02:55:46 -08:00
Andrew Waterman
ff2e47f380
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-03-09 02:08:55 -08:00
Yunsup Lee
a1b30282dd
major refactoring on vector exception interface
2012-03-09 01:09:22 -08:00
Yunsup Lee
8acbe98f53
change how fence.*.cv works, now control processor stalls on the fence instruction
2012-03-08 23:32:31 -08:00
Henry Cook
22726ae646
icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data
2012-03-08 18:47:32 -08:00
Henry Cook
4d2e7172f6
Added require_ack field to TransactionReply bundle
2012-03-08 18:07:44 -08:00
Henry Cook
35c4bd4084
Hub addr comparison bug fix
2012-03-08 16:39:05 -08:00
Henry Cook
788ad327da
Fixed dependency queue bug in Broadcast Hub
2012-03-08 11:36:10 -08:00
Henry Cook
7f43dee0c9
PriorityEncoder apply() no longer has recursive depth param
2012-03-08 01:04:26 -08:00
Andrew Waterman
5a7c5772a8
clearly distinguish PPN and cache tag
2012-03-07 23:11:17 -08:00
Andrew Waterman
941873bad1
coherence hub fixes
2012-03-07 21:03:44 -08:00
Henry Cook
7deff5fbe2
Broadcast hub bug fixes for load uncached mem req and store uncached xact rep
2012-03-07 11:40:49 -08:00
Andrew Waterman
c09eeb7fd2
fix D$ next-state logic
...
it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.
2012-03-07 01:42:08 -08:00
Andrew Waterman
a0c9452b86
change D$ to use FourStateCoherence protocol
...
instead of ThreeStateIncoherence.
2012-03-07 01:26:35 -08:00
Andrew Waterman
6e2610b0ad
fix Mux1H for bundles
2012-03-06 23:38:36 -08:00
Yunsup Lee
81dcb194d3
new vector exception interface
2012-03-06 22:39:15 -08:00
Henry Cook
47a2097507
unified coherence trait functions
2012-03-06 17:33:11 -08:00
Henry Cook
3dd404dcf4
hub code cleanup
2012-03-06 17:01:47 -08:00
Henry Cook
c0ed010bc9
newTransactionOnMiss()
2012-03-06 15:54:41 -08:00
Henry Cook
962e5a54af
Added store dependency queues to BroadcastHub. Minor improvements to utils.
2012-03-06 15:54:41 -08:00
Andrew Waterman
499c5b4a2e
automatically infer MEM_TAG_BITS
2012-03-06 15:49:28 -08:00
Andrew Waterman
6e16b04ada
implement transaction finish messages
2012-03-06 15:48:08 -08:00
Yunsup Lee
dba99e07a9
set MEM_TAG_BITS to 5 when HAVE_VEC is true, since NMSHR=4
2012-03-06 08:54:21 -08:00
Andrew Waterman
5f33ab24b0
fix merge conflict
...
oops :(
2012-03-06 02:02:53 -08:00
Andrew Waterman
5f12990dfb
support memory transaction aborts
2012-03-06 00:35:02 -08:00
Henry Cook
950b5cd900
Added aborted data dequeueing state machine for BroadcastHub
2012-03-05 17:44:30 -08:00
Henry Cook
5c66a6699c
Broadcast hub control logic bugfixes and code cleanup
2012-03-05 17:27:55 -08:00
Yunsup Lee
a950d526d2
add prefetch count queue
2012-03-05 12:09:41 -08:00
Yunsup Lee
d4ec7ff4d9
refined vector exception interface
2012-03-03 16:11:54 -08:00
Yunsup Lee
e28a551368
refactor code related to vector exceptions
...
- revisied interfaces
- new instructions
2012-03-03 15:15:00 -08:00
Yunsup Lee
f9fb3978ca
fix store prefetch bug, it no longer occupies an entry in the sdq
2012-03-03 15:14:59 -08:00
Henry Cook
1b3307df32
Removed has_data fields from all coherence messages, increased message type names to compensate
2012-03-02 23:51:53 -08:00
Henry Cook
35f97bf858
Filled out 4 state coherence functions for cache
2012-03-02 21:58:50 -08:00
Henry Cook
00989c58bd
Correction to probe reply w/ data handling
2012-03-02 17:20:22 -08:00
Andrew Waterman
1e1926ce63
flip direction of ioPipe to match ioDecoupled
2012-03-02 16:18:32 -08:00
Henry Cook
7406908d4a
BroadcastHub can be elaborated by C and vlsi backends
2012-03-02 12:19:27 -08:00
Yunsup Lee
54baa0713c
hack fence.g.cv to support waiting the control processor
2012-03-02 02:10:26 -08:00
Yunsup Lee
1054cec087
add vec countq interface
2012-03-02 00:43:32 -08:00
Yunsup Lee
8678b3d70c
clean up ioDecoupled/ioPipe interface
2012-03-01 20:48:46 -08:00
Andrew Waterman
6d03d75835
improve D$ internal interfaces
2012-03-01 20:20:15 -08:00
Andrew Waterman
28cacd953f
D$ cleanup - merge ReplayUnit and MSHRFile
2012-03-01 19:30:56 -08:00
Andrew Waterman
52101373e0
clean up D$ store data unit
2012-03-01 19:20:00 -08:00
Henry Cook
da39810bb2
Fixed elaboration errors in LockingArbiter and BoradcastHub. Fixed ioDecoupled direction error in XactTracker
2012-03-01 18:24:22 -08:00
Henry Cook
9d7707a0a2
Made xact_rep an ioValid, removed has_data member
2012-03-01 18:24:21 -08:00
Yunsup Lee
c7b01230f4
fix mul/div when waddr=0, can't believe torture didn't find this one
2012-03-01 10:15:27 -08:00
Henry Cook
c6162ac743
Unified hub ios. Fixed some hub elaboration errors.
2012-03-01 01:20:57 -08:00
Yunsup Lee
a8ef5e9e27
change NMSHR when HAVE_VEC is true
2012-03-01 01:07:47 -08:00
Yunsup Lee
6847160343
refactor arbiter priorities
2012-03-01 00:22:34 -08:00
Yunsup Lee
f641b44fb8
changes after the module uniquify bug fix
2012-02-29 22:00:59 -08:00
Henry Cook
813ffcbf3e
Finished broadcast hub with split mem req types. Untested.
2012-02-29 17:58:15 -08:00
Yunsup Lee
4939b72ba5
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-29 17:12:02 -08:00
Yunsup Lee
20d0088f66
temporary fix to match bit widths for Mem
2012-02-29 17:09:31 -08:00
Henry Cook
008ad1f45b
Added 'locking' arbiter that won't rearbitrate until the lock signal on the current winning input is low
2012-02-29 17:05:06 -08:00