riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Commit Graph

  • f191bb994c PatternPusher: can now expect a certain output (#952) Wesley W. Terpstra 2017-08-11 18:10:27 -07:00
  • baf769f924 tilelink: add PatternPusher, a device to inject a fixed traffic pattern (#950) Wesley W. Terpstra 2017-08-11 15:07:10 -07:00
  • a3358f34a0 Fix priority inversion for two back-to-back divides (#948) Andrew Waterman 2017-08-10 17:12:09 -07:00
  • fa867bc478 plusarg_reader: make synthesis path a no brainer (#947) Wesley W. Terpstra 2017-08-10 16:35:30 -07:00
  • 0a591c5b5b Roll back use of UIntToOH1 (#946) Andrew Waterman 2017-08-09 18:39:47 -07:00
  • 0b8b136831 Merge pull request #943 from freechipsproject/fix-ibuf Yunsup Lee 2017-08-09 10:38:35 -07:00
  • 721770244e Fix IBuf bug Andrew Waterman 2017-08-08 17:05:26 -07:00
  • fb2c22ca80 Merge pull request #944 from freechipsproject/fix-vlsi-mem-gen Yunsup Lee 2017-08-08 23:18:08 -07:00
  • 31b75987ca Avoid width warning Andrew Waterman 2017-08-08 20:57:31 -07:00
  • 8705b0e070 memgen: also randomize ren and rand register Yunsup Lee 2017-08-08 20:41:53 -07:00
  • 97ad528a32 Merge pull request #941 from freechipsproject/bump-riscv-tools Richard Xia 2017-08-08 18:50:29 -07:00
  • 49ba31ac34 Merge pull request #942 from freechipsproject/bus-blocker-lock Wesley W. Terpstra 2017-08-08 18:03:36 -07:00
  • a9b1410f01 BusBlocker: parameterize page granularity Wesley W. Terpstra 2017-08-08 17:10:01 -07:00
  • 010ba94474 BusBlocker: rename a variable Wesley W. Terpstra 2017-08-08 16:44:51 -07:00
  • 6d6fc38787 BusBlocker: lock bit should affect the prior PMP address, not next Wesley W. Terpstra 2017-08-08 16:43:59 -07:00
  • dd5934b6dc Bump riscv-tools to bump riscv-tests for mi-csr test fix and pull in stable binutils. Richard Xia 2017-08-08 15:58:55 -07:00
  • 0a351f677d Merge pull request #940 from freechipsproject/fix-ecc-way Yunsup Lee 2017-08-08 16:05:21 -07:00
  • 8cc41ab46b Merge pull request #936 from freechipsproject/vlsi-mem-gen Yunsup Lee 2017-08-08 16:04:53 -07:00
  • 809c7e8551 Don't merge stores that manifest WAW hazards Andrew Waterman 2017-08-08 15:12:40 -07:00
  • 3ef6e4c9f2 Merge pull request #939 from freechipsproject/bus-blocker Wesley W. Terpstra 2017-08-08 15:06:55 -07:00
  • 82e13443b2 Merge pull request #937 from freechipsproject/critical-paths Andrew Waterman 2017-08-08 15:03:28 -07:00
  • dd103ae7ec Merge pull request #938 from freechipsproject/dtim-ignore-cacheable Andrew Waterman 2017-08-08 15:00:13 -07:00
  • 8f261adc6b BusBlocker: change default policy to deny Wesley W. Terpstra 2017-08-08 14:19:59 -07:00
  • 0d76e96b88 tilelink: PMP controlled BusBlocker prevents bus accesses Wesley W. Terpstra 2017-08-07 18:30:38 -07:00
  • 7935c61c19 Don't report to the DTIM that data is cacheable Andrew Waterman 2017-08-08 11:55:04 -07:00
  • 74d309c18e Make I vs. D a static property of TLB, not an input pin Andrew Waterman 2017-08-08 11:52:35 -07:00
  • e92981b0bd DRY Andrew Waterman 2017-08-08 11:46:38 -07:00
  • 62ccba304c Perform tag error detectoin/correction in same cycle as RAM Andrew Waterman 2017-08-08 10:21:30 -07:00
  • 6d1d285464 Merge pull request #933 from freechipsproject/cinst Palmer Dabbelt 2017-08-07 21:40:10 -07:00
  • ea4b1bc349 Use vlsi_mem_gen for verilator flow Andrew Waterman 2017-08-07 20:36:22 -07:00
  • b0f32c8f09 Randomize disabled read ports in vlsi_mem_gen Andrew Waterman 2017-08-07 20:35:40 -07:00
  • cc1e2af336 Merge pull request #934 from freechipsproject/critical-paths Palmer Dabbelt 2017-08-07 19:41:08 -07:00
  • c8f8806df0 Merge pull request #932 from freechipsproject/tl-bus-delayer Henry Cook 2017-08-07 19:01:39 -07:00
  • c4092dd0cc tilelink: improve entropy of bus delayer Henry Cook 2017-08-07 17:36:07 -07:00
  • 402907990c Revert "Remove one gate from D$ ECC check" Andrew Waterman 2017-08-07 17:33:20 -07:00
  • 2910d6fa2a tilelink: make bus xbar protected so it can be suggestNamed Henry Cook 2017-08-07 17:30:24 -07:00
  • fc0d5fcf98 Print out the compressed instruction when executing one Palmer Dabbelt 2017-08-07 17:21:08 -07:00
  • e27072e063 Merge pull request #931 from freechipsproject/fix-ram-model-source-reuse Wesley W. Terpstra 2017-08-07 16:56:13 -07:00
  • c457c9cb9f tilelink: allow insertion of TLDelayer on TLBus outward node Henry Cook 2017-08-07 16:43:06 -07:00
  • d5a135914b Revert "Disable AMBAUnitTestConfig, as it is blocking unrelated PRs" Wesley W. Terpstra 2017-08-07 16:04:02 -07:00
  • 03002b3106 Merge pull request #930 from freechipsproject/fix-maskrom Yunsup Lee 2017-08-07 16:01:38 -07:00
  • f8b45564d1 tilelink: RAMModel must support source reuse Wesley W. Terpstra 2017-08-07 16:01:15 -07:00
  • 558fc7f293 maskrom: retain data for d channel is not ready Yunsup Lee 2017-08-07 12:17:10 -07:00
  • aff028f8f0 Merge pull request #926 from freechipsproject/bump-tools Yunsup Lee 2017-08-06 23:04:55 -07:00
  • 3d0051e799 bump tools for test fixes Andrew Waterman 2017-08-06 17:24:49 -07:00
  • 7fd8bb1159 Merge pull request #928 from freechipsproject/critical-paths Andrew Waterman 2017-08-06 18:50:59 -07:00
  • 658e36f98b Reduce fanout on frontend io.cpu.req.valid signal Andrew Waterman 2017-08-06 17:38:51 -07:00
  • 7d94074b05 Remove one gate from D$ ECC check Andrew Waterman 2017-08-06 17:36:53 -07:00
  • d03fdc4f30 diplomacy: seal the LazyModuleImpLike trait (#927) Wesley W. Terpstra 2017-08-06 17:32:23 -07:00
  • 5030a8b15a Merge pull request #925 from freechipsproject/fix-lazy-raw-modules Yunsup Lee 2017-08-06 14:42:14 -07:00
  • aa60c6944b diplomacy: provide default clock/reset for LazyRawModuleImp Yunsup Lee 2017-08-06 13:40:07 -07:00
  • 6389120dbd Merge pull request #923 from freechipsproject/critical-paths Yunsup Lee 2017-08-05 17:02:22 -07:00
  • 39b7e930ca Disable AMBAUnitTestConfig, as it is blocking unrelated PRs Andrew Waterman 2017-08-05 16:13:47 -07:00
  • 83875e3a0c Only flush D$ on FENCE.I if it won't always be probed on I$ miss Andrew Waterman 2017-08-05 13:47:21 -07:00
  • 991e16de92 Remove probe address mux from TLB response path Andrew Waterman 2017-08-05 12:57:38 -07:00
  • b9b4142bb4 Get s2_nack off the critical path Andrew Waterman 2017-08-05 00:30:36 -07:00
  • bc298bf146 Optimize ShiftQueue for late-arriving deq.ready Andrew Waterman 2017-08-04 22:06:37 -07:00
  • 6112adfbb0 Get L2 TLB tag/parity check off the D$ arbitration path Andrew Waterman 2017-08-04 17:01:51 -07:00
  • 8d97684555 Fix L2 TLB perfctr Andrew Waterman 2017-08-04 17:01:31 -07:00
  • df7f09b9ce Get I$ ECC check further off critical path Andrew Waterman 2017-08-04 14:59:56 -07:00
  • 4bfbe75d74 Avoid pipeline replays when fetch queue is full Andrew Waterman 2017-08-04 14:59:32 -07:00
  • a45997d03f Separate I$ parity error from miss signal Andrew Waterman 2017-08-04 00:37:13 -07:00
  • 06a831310b Shave a gate delay off I$ backpressure path Andrew Waterman 2017-08-04 00:40:18 -07:00
  • ecc2ee366c Shave a few gate delays off IBuf control logic Andrew Waterman 2017-08-04 00:39:10 -07:00
  • 82ff81e40d Merge pull request #924 from freechipsproject/dont-build-debug-verilog Andrew Waterman 2017-08-04 10:16:59 -07:00
  • 7937db0c84 Merge pull request #919 from freechipsproject/imiss-perf-counter Andrew Waterman 2017-08-04 01:04:23 -07:00
  • 21ac28b57a Don't build verilog twice for emulator and emulator-debug Andrew Waterman 2017-08-04 01:01:15 -07:00
  • 017ac130c1 Merge pull request #922 from freechipsproject/bigger_tl_xbar Megan Wachs 2017-08-03 16:52:56 -07:00
  • 50c85f1b62 TLXbar: Allow more masters and slaves and issue a warning. Megan Wachs 2017-08-03 15:39:18 -07:00
  • ba4eecc0f0 Use UIntToOH1 (#921) Andrew Waterman 2017-08-03 14:55:39 -07:00
  • f483bab4aa Fix I$ miss perfctr Andrew Waterman 2017-08-03 00:52:12 -07:00
  • 1be1433f04 Merge pull request #918 from freechipsproject/icache-prefetch Andrew Waterman 2017-08-02 21:22:20 -07:00
  • d66e8f8e80 Merge pull request #914 from freechipsproject/critical-paths Andrew Waterman 2017-08-02 19:05:31 -07:00
  • 3fc7100048 Merge pull request #917 from freechipsproject/fuzzer_order Megan Wachs 2017-08-02 18:39:59 -07:00
  • 2537d0d54e Optionally prefetch next I$ line into L2$ on miss Andrew Waterman 2017-08-02 17:10:35 -07:00
  • 744cdb2f72 Make TLB report when it's safe to prefetch within a page Andrew Waterman 2017-08-02 17:09:38 -07:00
  • d9821a74ce Merge pull request #916 from freechipsproject/transfer_sizes_print Megan Wachs 2017-08-02 16:56:36 -07:00
  • 595415d207 TLFuzzer: Correct the number of ordered clients created Megan Wachs 2017-08-02 15:48:21 -07:00
  • fc5c04ed4b TLFuzzer: Allow Ordered clients to be created as well by the fuzzer Megan Wachs 2017-08-02 14:44:18 -07:00
  • 7d2dd3769f Optimize a hazard check critical path Andrew Waterman 2017-08-02 11:49:43 -07:00
  • 85bdae0fa8 diplomacy: Pretty Print for TransferSizes Megan Wachs 2017-08-02 11:40:50 -07:00
  • 2eb239d03f Add option to retime D$ way mux into subsequent pipeline stage Andrew Waterman 2017-08-01 15:19:25 -07:00
  • 9464c6db40 Mitigate(?) frontend critical path Andrew Waterman 2017-08-01 18:21:03 -07:00
  • 735701382f Mitigate some I$ response valid critical paths Andrew Waterman 2017-08-01 15:24:58 -07:00
  • 2ecea2ef60 Don't use a pipe queue on D$ TL A-channel Andrew Waterman 2017-08-01 15:17:07 -07:00
  • f988b91575 Merge pull request #912 from freechipsproject/add-mask-rom Yunsup Lee 2017-07-31 22:28:11 -07:00
  • 6ef8ee5d4d tilelink: add mask rom Yunsup Lee 2017-07-31 21:12:45 -07:00
  • 4b33249812 Merge pull request #911 from freechipsproject/fix-dcache-bug Yunsup Lee 2017-07-31 19:14:16 -07:00
  • 42ff74bd34 Merge pull request #910 from freechipsproject/tilelink-map Wesley W. Terpstra 2017-07-31 18:33:09 -07:00
  • e140893a01 Use 1-entry queue on processor-side E-channel Andrew Waterman 2017-07-31 18:06:54 -07:00
  • 5681693ccc Fix a D$ ready-valid signaling regression Andrew Waterman 2017-07-31 18:05:14 -07:00
  • d7fd9d2b82 tilelink: Filter, add another case Wesley W. Terpstra 2017-07-31 16:51:11 -07:00
  • 71a250b071 Merge pull request #909 from freechipsproject/tile-buffer Yunsup Lee 2017-07-31 16:46:22 -07:00
  • b126105230 tilelink: add TLMap to make it possible to move slaves Wesley W. Terpstra 2017-07-31 16:29:20 -07:00
  • 13d3ffbcaa tilelink: Filter now support arbitrary filter functions Wesley W. Terpstra 2017-07-31 16:00:21 -07:00
  • 7adfd5c431 Merge pull request #906 from freechipsproject/critical-paths Yunsup Lee 2017-07-31 16:14:11 -07:00
  • 07b4edfc87 Merge pull request #908 from freechipsproject/combo-breaker Megan Wachs 2017-07-31 16:13:01 -07:00
  • f473e6bad0 tile: add optional boundary buffers Yunsup Lee 2017-07-31 15:40:54 -07:00
  • cb3529bbc3 util: tweak rational crossings to avoid mux in source Yunsup Lee 2017-07-30 22:31:19 -07:00
  • 11332c1226 dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative Henry Cook 2017-07-31 14:03:30 -07:00