Merge pull request #936 from freechipsproject/vlsi-mem-gen

Improve and use vlsi_mem_gen for verilator flow

Makefrag

@@ -10,6 +10,8 @@ CONFIG ?= DefaultConfig
 # TODO: For now must match rocketchip.Generator
 long_name = $(PROJECT).$(CONFIG)
 
+VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
+
 CXX ?= g++
 CXXFLAGS := -O1
 JVM_MEMORY ?= 2G

emulator/Makefrag-verilator

@@ -2,7 +2,9 @@
 # Verilator Generation
 #--------------------------------------------------------------------
 firrtl = $(generated_dir)/$(long_name).fir
-verilog = $(generated_dir)/$(long_name).v
+verilog = \
+  $(generated_dir)/$(long_name).v \
+  $(generated_dir)/$(long_name).behav_srams.v \
 
 .SECONDARY: $(firrtl) $(verilog)
 
@@ -10,9 +12,14 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
 	mkdir -p $(dir $@)
 	cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
-%.v: %.fir $(FIRRTL_JAR)
+%.v %.conf: %.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog
+	$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf
+
+$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN)
+	cd $(generated_dir) && \
+	$(VLSI_MEM_GEN) $(generated_dir)/$(long_name).conf > $@.tmp && \
+	mv -f $@.tmp $@
 
 # Build and install our own Verilator, to work around versionining issues.
 VERILATOR_VERSION=3.904
@@ -47,6 +54,7 @@ verilator: $(INSTALLED_VERILATOR)
 VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
 VERILATOR_FLAGS := --top-module $(MODEL) \
   +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+  +define+RANDOMIZE_GARBAGE_ASSIGN \
   +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
   --output-split 20000 \
   --output-split-cfuncs 20000 \
@@ -62,13 +70,13 @@ model_header_debug = $(generated_dir_debug)/$(long_name)/V$(MODEL).h
 $(emu): $(verilog) $(cppfiles) $(headers) $(INSTALLED_VERILATOR)
 	mkdir -p $(generated_dir)/$(long_name)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
-	-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
+	-o $(abspath $(sim_dir))/$@ $(verilog) $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(generated_dir) -include $(model_header)"
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
 
 $(emu_debug): $(verilog) $(cppfiles) $(headers) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
 	mkdir -p $(generated_dir_debug)/$(long_name)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name)  --trace \
-	-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
+	-o $(abspath $(sim_dir))/$@ $(verilog) $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug)"
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk

scripts/vlsi_mem_gen

@@ -89,19 +89,29 @@ def gen_mem(name, width, depth, mask_gran, mask_seg, ports):
   masked = len(maskedports)>0
   tup = (depth, width, nr, nw, nrw, masked)
 
-  for idx in range(nr):
-    prefix = 'R%d_' % idx
+  def emit_read(idx, rw):
+    prefix = ('RW%d_' if rw else 'R%d_') % idx
+    data = ('%srdata' if rw else '%sdata') % prefix
+    en = ('%sen && !%swmode' % (prefix, prefix)) if rw else ('%sen' % prefix)
+    decl.append('reg reg_%sren;' % prefix)
     decl.append('reg [%d:0] reg_%saddr;' % (addr_width-1, prefix))
     sequential.append('always @(posedge %sclk)' % prefix)
-    sequential.append('  if (%sen) reg_%saddr <= %saddr;' % (prefix, prefix, prefix))
-    combinational.append('assign %sdata = ram[reg_%saddr];' % (prefix, prefix))
+    sequential.append('  reg_%sren <= %s;' % (prefix, en))
+    sequential.append('always @(posedge %sclk)' % prefix)
+    sequential.append('  if (%s) reg_%saddr <= %saddr;' % (en, prefix, prefix))
+    combinational.append('`ifdef RANDOMIZE_GARBAGE_ASSIGN')
+    combinational.append('reg [%d:0] %srandom;' % (((width-1)//32+1)*32-1, prefix))
+    combinational.append('always @(posedge %sclk) %srandom <= {%s};' % (prefix, prefix, ', '.join(['$random'] * ((width-1)//32+1))))
+    combinational.append('assign %s = reg_%sren ? ram[reg_%saddr] : %srandom[%d:0];' % (data, prefix, prefix, prefix, width-1))
+    combinational.append('`else')
+    combinational.append('assign %s = ram[reg_%saddr];' % (data, prefix))
+    combinational.append('`endif')
+
+  for idx in range(nr):
+    emit_read(idx, False)
 
   for idx in range(nrw):
-    prefix = 'RW%d_' % idx
-    decl.append('reg [%d:0] reg_%saddr;' % (addr_width-1, prefix))
-    sequential.append('always @(posedge %sclk)' % prefix)
-    sequential.append('  if (%sen && !%swmode) reg_%saddr <= %saddr;' % (prefix, prefix, prefix, prefix))
-    combinational.append('assign %srdata = ram[reg_%saddr];' % (prefix, prefix))
+    emit_read(idx, True)
 
   for idx in range(len(latchports)):
     prefix = 'W%d_' % idx
@@ -123,13 +133,13 @@ def gen_mem(name, width, depth, mask_gran, mask_seg, ports):
   decl.append('  initial begin')
   decl.append('    #0.002 begin end')
   decl.append('    for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth)
-  decl.append('      ram[initvar] = {%d {$random}};' % ((width-1)/32+1))
+  decl.append('      ram[initvar] = {%d {$random}};' % ((width-1)//32+1))
   for idx in range(nr):
     prefix = 'R%d_' % idx
-    decl.append('    reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)/32+1)))
+    decl.append('    reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)//32+1)))
   for idx in range(nrw):
     prefix = 'RW%d_' % idx
-    decl.append('    reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)/32+1)))
+    decl.append('    reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)//32+1)))
   decl.append('  end')
   decl.append('`endif')
 

vsim/Makefile

@@ -11,7 +11,6 @@ default: all
 
 base_dir = $(abspath ..)
 generated_dir = $(abspath ./generated-src)
-VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
 mem_gen = $(VLSI_MEM_GEN)
 sim_dir = .
 output_dir = $(sim_dir)/output