riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

memgen: also randomize ren and rand register

Browse Source
This commit is contained in:
Yunsup Lee 2017-08-08 20:41:53 -07:00
parent 97ad528a32
commit 8705b0e070
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
scripts/vlsi_mem_gen
View File

@ -101,6 +101,13 @@ def gen_mem(name, width, depth, mask_gran, mask_seg, ports):
sequential.append(' if (%s) reg_%saddr <= %saddr;' % (en, prefix, prefix))
combinational.append('`ifdef RANDOMIZE_GARBAGE_ASSIGN')
combinational.append('reg [%d:0] %srandom;' % (((width-1)//32+1)*32-1, prefix))
combinational.append('`ifdef RANDOMIZE_MEM_INIT')
combinational.append(' initial begin')
combinational.append(' #0.002 begin end')
combinational.append(' reg_%sren = $random;' % prefix)
combinational.append(' %srandom = {%s};' % (prefix, ', '.join(['$random'] * ((width-1)//32+1))))
combinational.append(' end')
combinational.append('`endif')
combinational.append('always @(posedge %sclk) %srandom <= {%s};' % (prefix, prefix, ', '.join(['$random'] * ((width-1)//32+1))))
combinational.append('assign %s = reg_%sren ? ram[reg_%saddr] : %srandom[%d:0];' % (data, prefix, prefix, prefix, width-1))
combinational.append('`else')