riscv/rocket-chip
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Merge pull request #938 from freechipsproject/dtim-ignore-cacheable

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Don't report to the DTIM that data is cacheable
This commit is contained in:
Andrew Waterman 2017-08-08 15:00:13 -07:00 committed by GitHub
commit dd103ae7ec
4 changed files with 7 additions and 10 deletions
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5
src/main/scala/rocket/DCache.scala
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@ -144,7 +144,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false }
// address translation
val tlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> tlb.io.ptw
tlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence)
tlb.io.req.bits.sfence.valid := s1_sfence
@ -154,7 +154,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
tlb.io.req.bits.sfence.bits.addr := s1_req.addr
tlb.io.req.bits.passthrough := s1_req.phys
tlb.io.req.bits.vaddr := s1_req.addr
tlb.io.req.bits.instruction := false
tlb.io.req.bits.size := s1_req.typ
tlb.io.req.bits.cmd := s1_req.cmd
when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false }
@ -201,7 +200,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (s1_valid_not_nacked || s1_flush_valid) {
s2_req := s1_req
s2_req.addr := s1_paddr
s2_uncached := !tlb.io.resp.cacheable || Bool(usingDataScratchpad)
s2_uncached := !tlb.io.resp.cacheable
}
val s2_read = isRead(s2_req.cmd)
val s2_write = isWrite(s2_req.cmd)

3
src/main/scala/rocket/Frontend.scala
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@ -82,7 +82,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
val fetchBytes = coreInstBytes * fetchWidth
val tlb = Module(new TLB(log2Ceil(fetchBytes), nTLBEntries))
val tlb = Module(new TLB(true, log2Ceil(fetchBytes), nTLBEntries))
val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) }
val s0_valid = io.cpu.req.valid || !fq.io.mask(fq.io.mask.getWidth-3)
@ -130,7 +130,6 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
tlb.io.req.valid := !s2_replay
tlb.io.req.bits.vaddr := s1_pc
tlb.io.req.bits.passthrough := Bool(false)
tlb.io.req.bits.instruction := Bool(true)
tlb.io.req.bits.sfence := io.cpu.sfence
tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth)

3
src/main/scala/rocket/NBDcache.scala
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@ -700,7 +700,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
// check for unsupported operations
assert(!s1_valid || !s1_req.cmd.isOneOf(M_PWR))
val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
val dtlb = Module(new TLB(false, log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> dtlb.io.ptw
dtlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence)
dtlb.io.req.bits.sfence.valid := s1_sfence
@ -710,7 +710,6 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
dtlb.io.req.bits.sfence.bits.asid := io.cpu.s1_data.data
dtlb.io.req.bits.passthrough := s1_req.phys
dtlb.io.req.bits.vaddr := s1_req.addr
dtlb.io.req.bits.instruction := Bool(false)
dtlb.io.req.bits.size := s1_req.typ
dtlb.io.req.bits.cmd := s1_req.cmd
when (!dtlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := Bool(false) }

6
src/main/scala/rocket/TLB.scala
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@ -52,7 +52,7 @@ class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
val prefetchable = Bool()
}
class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val req = Decoupled(new TLBReq(lgMaxSize)).flip
val resp = new TLBResp().asOutput
@ -92,7 +92,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
val r_refill_waddr = Reg(UInt(width = log2Ceil(normalEntries)))
val r_req = Reg(new TLBReq(lgMaxSize))
val priv = Mux(io.req.bits.instruction, io.ptw.status.prv, io.ptw.status.dprv)
val priv = if (instruction) io.ptw.status.prv else io.ptw.status.dprv
val priv_s = priv(0)
val priv_uses_vm = priv <= PRV.S
val vm_enabled = Bool(usingVM) && io.ptw.ptbr.mode(io.ptw.ptbr.mode.getWidth-1) && priv_uses_vm && !io.req.bits.passthrough
@ -113,7 +113,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_)
def fastCheck(member: TLManagerParameters => Boolean) =
legal_address && edge.manager.fastProperty(mpu_physaddr, member, (b:Boolean) => Bool(b))
val cacheable = fastCheck(_.supportsAcquireB)
val cacheable = fastCheck(_.supportsAcquireB) && (instruction || !usingDataScratchpad)
val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits)(mpu_physaddr).homogeneous
val prot_r = fastCheck(_.supportsGet) && pmp.io.r
val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w